AD7854 Analog Devices, AD7854 Datasheet - Page 8

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7854/AD7854L
AD7854/AD7854L ON-CHIP REGISTERS
The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the
AD7854/AD7854L will operate as a read-only ADC. The WR pin should be tied to DV
read-only ADC.
Extra features and flexibility such as performing different power-down options, different types of calibrations including system cali-
bration, and software conversion start can be selected by writing to the part.
The AD7854/AD7854L contains a control register, ADC output data register, status register, test register and 10 calibra-
tion registers. The control register is write-only, the ADC output data register and the status register are read-only, and the test and
calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing
To write to the AD7854/AD7854L, a 16-bit word of data must be transferred. This transfer consists of two 8-bit writes. The first
8 bits of data that are written must consist of the 8 LSBs of the 16-bit word and the second 8 bits that are written must consist of the
8 MSBs of the 16-bit word. For each of these 8-bit writes, the data is placed on Pins DB0 to DB7, Pin DB0 being the LSB of each
transfer and Pin DB7 being the MSB of each transfer. The two MSBs of the 16-bit word, ADDR1 and ADDR0, are decoded to
determine which register is addressed, and the 14 LSBs are written to the addressed register. Table I shows the decoding of the
address bits, while Figure 2 shows the overall write register hierarchy.
ADDR1
0
0
1
1
Reading
To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These
bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address
bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be
from the ADC output data register. Note: when reading from the calibration registers, the low byte must always be read first.
Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register
until the read selection bits are changed in the control register.
RDSLT1
0
0
1
1
Figure 2. Write Register Hierarchy/Address Decoding
CALSLT1, CALSLT0
DECODE
RDSLT0
0
1
0
1
ADDR0
0
1
0
1
OFFSET(1)
REGISTER
GAIN(1)
DAC(8)
00
01
TEST
This combination does not address any register.
This combination addresses the TEST REGISTER. The 14 LSBs of data are written to the test register.
This combination addresses the CALIBRATION REGISTER. The 14 least significant data bits are writ-
ten to the selected calibration register.
This combination addresses the CONTROL REGISTER. The 14 least significant data bits are written to
the control register.
Comment
All successive read operations are from the ADC OUTPUT DATA REGISTER. This is the default power-
up setting. There is always four leading zeros when reading from the ADC output data register.
All successive read operations are from the TEST REGISTER.
All successive read operations are from the CALIBRATION REGISTERS.
All successive read operations are from the STATUS REGISTER.
Comment
OFFSET(1)
GAIN(1)
01
ADDR1, ADDR0
CALIBRATION
REGISTERS
DECODE
10
OFFSET(1)
10
Table II. Read Register Addressing
Table I. Write Register Addressing
REGISTER
CONTROL
GAIN(1)
11
11
–8–
Figure 3. Read Register Hierarchy/Address Decoding
DATA REGISTER
CALSLT1, CALSLT0
ADC OUTPUT
00
DECODE
DD
OFFSET(1)
REGISTER
GAIN(1)
DAC(8)
00
01
for operating the AD7854/AD7854L as a
TEST
OFFSET(1)
GAIN(1)
01
RDSLT1, RDSLT0
CALIBRATION
REGISTERS
DECODE
10
OFFSET(1)
10
REGISTER
CONTROL
GAIN(1)
11
11
REV. B