AD5737 Analog Devices, AD5737 Datasheet - Page 28

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
DAC Control Register
The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 22 and Table 23.
Table 22. Programming the DAC Control Register
D15
0
1
Table 23. DAC Control Register Bit Descriptions
Bit Name
INT_ENABLE
CLR_EN
OUTEN
RSET
DC_DC
R2, R1, R0
X = don’t care.
D14
1
D13
0
Description
Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. This bit applies to individual
channels only; it does not enable the output. After setting this bit, it is recommended that a >200 μs delay be observed
before enabling the output to reduce the output enable glitch. See Figure 24 for plots of this glitch.
Per-channel clear enable bit. This bit specifies whether the selected channel is cleared when the CLEAR pin is activated.
0 = channel is not cleared when the part is cleared (default).
1 = channel is cleared when the part is cleared.
Enables or disables the selected output channel.
0 = channel disabled (default).
1 = channel enabled.
Selects the internal current sense resistor or an external current sense resistor for the selected DAC channel.
0 = external resistor selected (default).
1 = internal resistor selected.
Powers up or powers down the dc-to-dc converter on the selected channel. All dc-to-dc converters can be powered up
simultaneously using the DCDC_ALL bit in the main control register. To power down the dc-to-dc converter, the OUTEN
and INT_ENABLE bits must also be set to 0.
0 = dc-to-dc converter is powered down (default).
1 = dc-to-dc converter is powered up.
Selects the output range to be enabled.
R2
0
0
0
0
1
1
1
D12
X
1
D11
X
1
R1
0
0
1
1
0
0
1
D10
X
1
D9
X
1
R0
0
1
0
1
0
1
0
D8
INT_ENABLE CLR_EN OUTEN
Rev. A | Page 28 of 44
Output Range Selected
Reserved
Reserved
Reserved
Reserved
4 mA to 20 mA current range
0 mA to 20 mA current range
0 mA to 24 mA current range
D7
D6
D5
RSET
D4
DC_DC
D3
X
1
D2
R2
Data Sheet
D1
R1
D0
R0