AD5737 Analog Devices, AD5737 Datasheet - Page 32

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
DEVICE FEATURES
FAULT OUTPUT
The
open-drain output that allows several
connected together to one pull-up resistor for global fault
detection. The
following fault conditions:
•
•
•
The I
register are used in conjunction with the FAULT output to
inform the user which fault condition caused the FAULT
output to be activated.
DIGITAL OFFSET AND GAIN CONTROL
Each DAC channel has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the DAC data register is
operated on by a digital multiplier and adder controlled by the
contents of the gain and offset registers; the calibrated DAC
data is then stored in the DAC input register (see Figure 52).
Although Figure 52 indicates a multiplier and adder for each
channel, the device has only one multiplier and one adder,
which are shared by all four channels. This design has impli-
cations for the update speed when several channels are updated
at once (see Table 3).
AD5737
The voltage at I
range due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with windowed
limits because this requires an actual output error before
the FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output stage
has less than approximately 1 V of remaining drive
capability. Thus, the FAULT output is activated slightly
before the compliance limit is reached.
An interface error is detected due to a PEC failure (see the
Packet Error Checking section).
The core temperature of the
mately 150°C.
OUT_x
OFFSET (C)
REGISTER
REGISTER
DAC DATA
REGISTER
fault, PEC error, and over temp bits of the status
GAIN (M)
is equipped with a FAULT pin, an active low,
Figure 52. Digital Offset and Gain Control
FAULT pin is forced active by any one of the
OUT_x
attempts to rise above the compliance
AD5737
REGISTER
INPUT
AD5737
DAC
exceeds approxi-
devices to be
DAC
Rev. A | Page 32 of 44
When data is written to the gain (M) or offset (C) register, the
output is not automatically updated. Instead, the next write to
the DAC channel uses the new gain and offset values to perform
a new calibration and automatically updates the channel.
The output data from the calibration is routed to the DAC input
register. This data is then loaded to the DAC, as described in the
Serial Interface section. Both the gain register and the offset
register have 12 bits of resolution. The correct order to calibrate
the gain and offset is to first calibrate the gain and then calibrate
the offset.
The value (in decimal) that is written to the DAC input register
can be calculated as follows:
where:
D is the code loaded to the DAC data register of the
DAC channel.
M is the code in the gain register (default code = 2
C is the code in the offset register (default code = 2
STATUS READBACK DURING A WRITE
The
the status register during every write sequence. This feature is
enabled using the STATREAD bit in the main control register.
When this feature is enabled, the user can continuously monitor
the status register and act quickly in the case of a fault.
When status readback during a write is enabled, the contents
of the 16-bit status register (see Table 32) are output on the SDO
pin, as shown in Figure 5.
When the
write feature is disabled. When this feature is enabled, readback
of registers other than the status register is not available. To read
back any other register, clear the STATREAD bit before following
the readback sequence (see the Readback Operation section).
The STATREAD bit can be set high again after the register read.
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge sensitive input that allows the
output to be cleared to a preprogrammed 12-bit code. This code
is user-programmable via a per-channel 12-bit clear code register.
For a channel to be cleared, set the CLR_EN bit in the DAC
control register for that channel. If the clear function on a
channel is not enabled, the output remains in its current state,
independent of the level of the CLEAR pin.
When the CLEAR signal returns low, the relevant outputs remain
cleared until a new value is programmed to them.
AD5737
Code
DACRegiste
AD5737
can be configured to read back the contents of
r
=
is powered up, the status readback during a
D
×
(
M
2
12
+
) 1
+
C
−
2
11
Data Sheet
12
11
− 1).
).
(1)