AD5737 Analog Devices, AD5737 Datasheet - Page 31

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

MSB
D15
DC-DCD DC-DCC DC-DCB DC-DCA User
Data Sheet
Status Register
The status register is a read-only register. This register contains
any fault information, as a well as a ramp active bit (Bit D9) and
a user toggle bit (Bit D11). When the STATREAD bit in the
main control register is set, the status register contents can be
Table 31. Decoding the Status Register
1
Table 32. Status Register Bit Descriptions
Bit Name
DC-DCD
DC-DCC
DC-DCB
DC-DCA
User Toggle
PEC Error
Ramp Active
Over Temp
I
I
I
I
OUT_D
OUT_C
OUT_B
OUT_A
X = don’t care.
Fault
Fault
Fault
Fault
D14
Description
This bit is set if the dc-to-dc converter on Channel D cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its V
more information about the operation of this bit under this condition.
This bit is set if the dc-to-dc converter on Channel C cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its V
more information about the operation of this bit under this condition.
This bit is set if the dc-to-dc converter on Channel B cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its V
more information about the operation of this bit under this condition.
This bit is set if the dc-to-dc converter on Channel A cannot maintain compliance, for example, if the dc-to-dc converter is
reaching its V
more information about the operation of this bit under this condition.
User toggle bit. This bit is set or cleared via the software register and can be used to verify data communications, if needed.
Denotes a PEC error on the last data-word received over the SPI interface.
This bit is set while any output channel is slewing (digital slew rate control is enabled on at least one channel).
This bit is set if the
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
This bit is set if a fault is detected on the I
D13
MAX
MAX
MAX
MAX
D12
voltage; in this case, the I
voltage; in this case, the I
voltage; in this case, the I
voltage; in this case, the I
AD5737
D11
toggle
core temperature exceeds approximately 150°C.
D10
PEC
error
D9
Ramp
active
OUT_D
OUT_C
OUT_B
OUT_A
OUT_D
OUT_C
OUT_B
OUT_A
Rev. A | Page 31 of 44
pin.
pin.
pin.
pin.
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
fault bit is also set. See the DC-to-DC Converter V
D8
Over
temp
D7
X
read back on the SDO pin during every write sequence. Alterna-
tively, if the STATREAD bit is not set, the status register can be
read using the normal readback operation (see the Readback
Operation section).
1
D6
X
1
D5
X
1
D4
X
1
D3
I
fault
OUT_D
MAX
MAX
MAX
MAX
Functionality section for
Functionality section for
Functionality section for
Functionality section for
D2
I
fault
OUT_C
D1
I
fault
OUT_B
AD5737
LSB
D0
I
fault
OUT_A