AD5755 Analog Devices, AD5755 Datasheet - Page 41

• Manufacturer Part Number: AD5755
• Description: Quad Channel, 16-Bit, Serial Input,
• Manufacturer: Analog Devices

Specifications of AD5755

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

Data Sheet
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge-sensitive input that allows the
output to be cleared to a preprogrammed 16-bit code. This code
is user programmable via a per channel 16-bit clear code register.
For a channel to clear, that channel must be enabled to be
cleared via the CLR_EN bit (see Table 21) in the channel’s DAC
control register. If the channel is not enabled to be cleared, then
the output remains in its current state independent of the
CLEAR pin level.
When the CLEAR signal is returned low, the relevant outputs
remain cleared until a new value is programmed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5755 offers the option of packet error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5755 should generate an 8-bit frame check
sequence using the polynomial
This is added to the end of the data-word, and 32 bits are sent
to the AD5755 before taking SYNC high. If the AD5755 sees a
32-bit frame, it performs the error check when SYNC goes high.
If the check is valid, the data is written to the selected register.
If the error check fails, the FAULT pin goes low and the PEC
error bit in the status register is set. After reading the status
register, FAULT returns high (assuming there are no other
faults), and the PEC error bit is cleared automatically.
FAULT
The PEC can be used for both transmit and receive of data
packets. If status readback during a write is enabled, the PEC
values returned during the status readback during a write
operation should be ignored. If status readback during a write is
SYNC
SCLK
SYNC
SCLK
SDIN
SDIN
C(x) = x
MSB
D23
MSB
D31
32-BIT DATA TRANSFER WITH ERROR CHECKING
24-BIT DATA TRANSFER—NO ERROR CHECKING
8
+ x
2
+ x
UPDATE ON SYNC HIGH
1
24-BIT DATA
24-BIT DATA
Figure 77. PEC Timing
+ 1
ONLY IF ERROR CHECK PASSED
LSB
LSB
UPDATE ON SYNC HIGH
D0
D8
IF ERROR CHECK FAILS
FAULT PIN GOES LOW
D7
8-BIT CRC
D0
Rev. A | Page 41 of 52
disabled, the user can still use the normal readback operation to
monitor status register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 has not been written to the software register
within the programmed timeout period. This feature is useful to
ensure that communication has not been lost between the MCU
and the AD5755 and that these datapath lines are working
properly (that is, SDI, SCLK, and SYNC ). If 0x195 is not
received by the software register within the timeout period, the
ALERT pin signals a fault condition. The ALERT signal is active
high and can be connected directly to the CLEAR pin to enable
a clear in the event that communication from the MCU is lost.
The watchdog timer is enabled, and the timeout period (5 ms,
10 ms, 100 ms, or 200 ms) is set in the main control register (see
Table 18 and Table 19).
OUTPUT ALERT
The AD5755 is equipped with an ALERT pin. This is an active
high CMOS output. The AD5755 also has an internal watchdog
timer. When enabled, it monitors SPI communications. If 0x195
is not received by the software register within the timeout period,
the ALERT pin goes active.
INTERNAL REFERENCE
The AD5755 contains an integrated 5 V voltage reference with
initial accuracy of ±5 mV maximum and a temperature drift
coefficient of ±10 ppm maximum. The reference voltage
is buffered and externally available for use elsewhere within
the system.
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 72, R
of the voltage-to-current conversion circuitry. The stability of
the output current value over temperature is dependent on the
stability of the value of R
stability of the output current over temperature, an external
15 kΩ low drift resistor can be connected to the R
AD5755 to be used instead of the internal resistor, R1. The
external resistor is selected via the DAC control register (see
Table 20).
Table 1 outlines the performance specifications of the AD5755
with both the internal R
resistor. Using an external R
performance over the internal R
R
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output, and thus the total unadjusted error. To arrive at
the gain/TUE error of the output with a particular external R
resistor, add the percentage absolute error of the R
directly to the gain/TUE error of the AD5755 with the external
R
SET
SET
resistor specification assumes an ideal resistor; the actual
resistor, shown in Table 1 (expressed in % FSR).
SET
SET
SET
resistor and an external, 15 kΩ R
. As a method of improving the
is an internal sense resistor as part
SET
resistor allows for improved
SET
resistor option. The external
SET_x
SET
AD5755
resistor
pin of the
SET
SET