AD5755 Analog Devices, AD5755 Datasheet - Page 9

• Manufacturer Part Number: AD5755
• Description: Quad Channel, 16-Bit, Serial Input,
• Manufacturer: Analog Devices

Specifications of AD5755

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

Data Sheet
TIMING CHARACTERISTICS
AV
GNDSW
otherwise noted.
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Guaranteed by design and characterization; not production tested.
All input signals are specified with t
See Figure 3, Figure 4, Figure 5, and Figure 6.
This specification applies if LDAC is held low during the write cycle; otherwise, see t
4
DD
= V
x
BOOST_x
= 0 V; REFIN = 5 V; voltage outputs: R
1, 2, 3
= 15 V; AV
Limit at T
33
13
13
13
13
198
5
5
20
5
10
500
See the AC Performance
Characteristics section
10
5
40
21
5
500
800
20
5
SS
MIN
= −15 V; DV
RISE
, T
= t
MAX
FALL
= 5 ns (10% to 90% of DV
DD
= 2.7 V to 5.5 V; AV
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
μs min
ns min
ns max
μs max
ns min
μs max
ns max
μs min
μs min
ns min
ns min
μs min
μs min
L
= 1 kΩ, C
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
DD
th
L
) and timed from a voltage level of 1.2 V.
Rev. A | Page 9 of 52
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= 220 pF; current outputs: R
nd
CC
SCLK falling edge to SYNC rising edge (see
= 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =
9
.
L
= 300 Ω; all specifications T
Figure 77
)
MIN
to T
AD5755
MAX
, unless