AD9125 Analog Devices, AD9125 Datasheet
AD9125
Specifications of AD9125
Related parts for AD9125
AD9125 Summary of contents
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... ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface allows programming/readback of many inter- nal parameters. Full-scale output current can be programmed over a range of 8 31.7 mA. The AD9125 comes in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. ...
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... AD9125 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 Digital Specifications ................................................................... 5 Latency and Power-Up Timing Specifications ......................... 5 AC Specifications .......................................................................... 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ...
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... SERIAL PROGRAMMING INPUT/OUTPUT REGISTERS PORT 16 I OFFSET NCO 10 AND HB2 HB3 Q OFFSET MOD 16 SYNC POWER-ON MULTICHIP RESET SYNCHRONIZATION Figure 2. AD9125 Functional Block Diagram Rev Page 1.2G AUX DAC 1 16-BIT INV DACCLK SINC 16 1.2G AUX DAC 1 16-BIT REF 10 10 AND BIAS DAC CLK_SEL ...
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... AD9125 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) 1 Full-Scale Output Current Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ± ...
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... IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3V Self biased input, ac couple 1 GHz ≤ f ≤ 2.1 GHz VCO See the Multichip Synchronization section for conditions Min Rev Page AD9125 = 20 mA, maximum sample rate, unless Min Typ Max 1.2 0.6 250 1.4 1.8 2.0 0.4 0.4 0.4 1.2 1.6 2.4 0.6 ...
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... AD9125 AC SPECIFICATIONS AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR 100 MSPS MHz DAC OUT f = 200 MSPS MHz DAC OUT f = 400 MSPS MHz DAC OUT f = 800 MSPS MHz DAC OUT TWO-TONE INTERMODULATION DISTORTION (IMD) ...
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... V to AVDD33 + 0.3 V −0 DVDD18 + 0.3 V −0 CVDD18 + 0.3 V −0 IOVDD + 0.3 V 125°C −65°C to +150°C Rev Page θ , and θ values are specified for a 4-layer board θ θ θ Unit 20.7 10.9 1.1 °C/W AD9125 Conditions EPAD soldered ...
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... D18 Data Bit 18. 25 D17 Data Bit 17. 26 D16 Data Bit 16. 27 DCI Data Clock Input. 1 PIN 1 2 INDICATOR 3 CVSS 4 FRAME IRQ 7 AD9125 D31 8 D30 9 TOP VIEW (Not to Scale IOVDD 11 12 D29 13 D28 14 D27 15 D26 16 D25 17 D24 18 Figure 3. Pin Configuration Rev ...
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... CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 72 CVDD18 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. EPAD Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB. Rev Page AD9125 ...
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... AD9125 TYPICAL PERFORMANCE CHARACTERISTICS 125MSPS, SECOND HARMONIC DATA f = 125MSPS, THIRD HARMONIC –10 DATA f = 250MSPS, SECOND HARMONIC DATA – 250MSPS, THIRD HARMONIC DATA –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 f (MHz) OUT Figure 4. Harmonics vs. f over f OUT ...
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... DATA f = 101MHz OUT VBW 10kHz STOP 500.0MHz SWEEP 6.017s (601 PTS) Figure 14. 4× Interpolation, Single-Tone Spectrum 8× INTERPOLATION, SINGLE-TONE SPECTRUM 125MSPS, DATA f = 131MHz OUT VBW 10kHz STOP 1.0GHz SWEEP 12.05s (601 PTS) Figure 15. 8× Interpolation, Single-Tone Spectrum AD9125 ...
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... AD9125 – 125MSPS DATA f = 250MSPS DATA –55 –60 –65 –70 –75 –80 –85 – 100 150 f (MHz) OUT Figure 16. IMD vs. f over f , 2× Interpolation, OUT DATA Digital Scale = 0 dBFS – 125MSPS DATA f = 250MSPS DATA –55 –60 –65 –70 – ...
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... Digital Scale, f OUT DATA 4× Interpolation mA, PLL Off SC f 8×, = 125MSPS DATA 0 100 200 300 400 500 f (MHz) OUT over Interpolation Rate and f OUT Digital Scale = 0 dBFS mA, PLL On SC AD9125 450 500 , DATA 250 = 200 MSPS, 600 , DATA ...
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... AD9125 –77 0dBFS –3dBFS –78 –6dBFS –79 –80 –81 –82 –83 – 100 150 f (MHz) OUT Figure 28. One-Carrier W-CDMA ACLR vs. f Adjacent Channel, PLL Off –78 0dBFS –3dBFS –6dBFS –80 –82 –84 –86 –88 – 100 150 f (MHz) OUT Figure 29 ...
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... REF CARRIER POWER: –16.89dBm/3.84000MHz –85.24 –95.25 –85.43 –95.43 1 –16.92dBm 2 –16.89dBm 3 –17.43dBm 4 –17.64dBm Figure 35. One-Carrier W-CDMA ACLR Performance, IF ≈150 MHz Rev Page AD9125 VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) LOWER UPPER OFFSET FREQ INTEG BW dBc ...
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... AD9125 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... THEORY OF OPERATION The AD9125 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9125 allows wider bandwidths and more carriers to be synthesized than in previously available DACs ...
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... AD9125 SERIAL PORT OPTIONS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte ...
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... NCO gain Bypass Select Send I data phase sideband to Q data compen- sation and dc offset HB1[1:0] Bypass HB1 Bypass HB2 Bypass HB3 AD9125 Default 0x00 0x10 0x00 0x00 0x00 N/A N/A 1 0x3F 0x40 0xD1 0xD9 0x00 0x00 0x48 0x00 ...
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... AD9125 Addr Register Name (Hex) Bit 7 FTW 1 (LSB) 0x30 FTW 2 0x31 FTW 3 0x32 FTW 4 (MSB) 0x33 NCO Phase Offset 0x34 LSB NCO Phase Offset 0x35 MSB NCO FTW Update 0x36 I Phase Adj LSB 0x38 I Phase Adj MSB 0x39 Q Phase Adj LSB ...
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... Enable sync phase locked Enable soft FIFO sync 1 = enables interrupt for soft FIFO reset. Rev Page Bit 3 Bit 2 Bit 1 Bit 0 AD9125 Default 0xAA 0x00 0x00 0x00 0x00 0x0C Default 0 0 ...
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... AD9125 Register Address Name (Hex) Bits 1 0 Interrupt Enable 2 0x05 Event Flag 1 0x06 Event Flag 2 0x07 Clock Receiver 0x08 7 Control Name Description Enable FIFO Warning enables interrupt for FIFO Warning 1. ...
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... Sync averaging[2:0] Sets the number of input samples that are averaged for determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. Rev Page 16 16. AD9125 Default 110 10001 ...
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... AD9125 Register Address Name (Hex) Bits Sync Control 2 0x11 5:0 Sync Status 1 0x12 7 6 Sync Status 2 0x13 [7:0] FIFO Control 0x17 [2:0] FIFO Status 1 0x18 FIFO Status 2 0x19 [7:0] Datapath Control 0x1B Name Description 110 = 64. 111 = 128. Sync phase request[5:0] This sets the requested clock phase offset after sync. ...
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... Bypass HB3 1 = bypasses third-stage interpolation filter. Chip ID[7:0] This register identifies the device as an AD9125. Rev Page AD9125 . IN1 . IN1 ; filter pass band is IN1 ...
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... AD9125 Register Address Name (Hex) Bits FTW 1 (LSB) 0x30 [7:0] FTW 2 0x31 [7:0] FTW 3 0x32 [7:0] FTW 4 (MSB) 0x33 [7:0] NCO Phase Offset 0x34 [7:0] LSB NCO Phase Offset 0x35 [7:0] MSB NCO FTW Update 0x36 Phase Adj LSB 0x38 [7:0] I Phase Adj MSB 0x39 [1:0] Q Phase Adj LSB ...
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... Die temp[7:0] Die Temp[15:0] indicates the approximate die temperature. 0xADCC = −39.9°C. 0xC422 = 25.1°C. … 0xD8A8 = 84.8°C (see the Temperature Sensor section for details). Die temp[15:8] See Register 0x49. Rev Page AD9125 Default ...
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... AD9125 Register Address Name (Hex) Bits SED Control 0x67 Compare I0 LSBs 0x68 [7:0] Compare I0 MSBs 0x69 [7:0] Compare Q0 LSBs 0x6A [7:0] Compare Q0 MSBs 0x6B [7:0] Compare I1 LSBs 0x6C [7:0] Compare I1 MSBs 0x6D [7:0] Compare Q1 LSBs 0x6E [7:0] Compare Q1 MSBs 0x6F [7:0] SED I LSBs 0x70 [7:0] SED I MSBs 0x71 ...
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... CMOS INPUT DATA PORTS The AD9125 input data port consists of a data clock (DCI), data bus, and FRAME signal. The data port can be configured to operate in three modes: dual-word mode, word mode, and byte mode. In dual-word mode, I and Q data is received simultaneously on two 16-pin buses. One bus receives I datapath input words, and the other bus receives Q datapath input words ...
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... See the Interface Timing Validation section for details. FIFO OPERATION The AD9125 contains a 2-channel, 16-bit wide, eight-word-deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock ...
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... DCI and the main DACCLK, the FIFO level value can be off by ±1 count. Therefore important to keep the difference between the read and write pointers to at least 2. Rev Page AD9125 ...
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... AD9125 DIGITAL DATAPATH The block diagram in Figure 50 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band interpolation filters, a quadrature modulator with a fine resolution NCO, a phase and offset adjustment block, and an inverse sinc filter. PREMOD HB1 HB2 HB3 Figure 50 ...
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... NORMALIZED FREQUENCY (× IN2 Figure 53. HB2, Even Filter Modes MODE 1 MODE 5 MODE 3 0 –20 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 f NORMALIZED FREQUENCY (× IN2 Figure 54. HB2, Odd Filter Modes AD9125 MODE 6 1.6 1 MODE 7 1.6 1 the filter. IN2 . IN2 ...
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... AD9125 Table 18 summarizes the HB2 and HB3 modes. Table 18. HB2 and HB3 Filter Mode Summary Mode f f Input Data CENTER MOD 0 DC None Real or complex None Complex None Complex None Complex Real or complex IN IN ...
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... FTW registers with the desired values, Bit 0 of Register 0x36 must transition from for the new FTW to take effect. DATAPATH CONFIGURATION Configuring the AD9125 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. ...
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... AD9125 HB1, HB2, AND HB3 0.8 0.6 0.5 0.1 0.4 0.6 0.25 0. OUT DATA Figure 59. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 21. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) Interpolation Factor HB1[ (2) ...
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... BW • f CENTER As shown in Figure 58, the value at 0.7 × f calculated as 0.8 − 2(0.7 − 0.6) = 0.6. Therefore, the AD9125 supports a bandwidth of 60 required 56%. The signal center frequency is 0.7 × f input signal is at baseband, the frequency shift required is also . DATA 0.7 × f column in the 4× interpolation section in Table 21 selects the filter modes that give a center frequency of f frequency translation ...
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... AD9125 DATA RATES VS. INTERPOLATION MODES Table 23 summarizes the maximum bus speed (f supported input data rates, and the signal bandwidths for various combinations of bus width modes and interpolation rates. The maximum bus speed in any mode is 250 MHz. The maximum DAC update rate ( any mode is 1000 MHz ...
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... Figure 61. DAC Output Currents vs. DAC Offset Value −1 ) filter is a nine-tap FIR filter. The −1 and the sin(x)/x response of 0.1 0.2 0.3 0 OUT DAC −1 Filter with Sin(x)/x Roll-Off filter is enabled by default. It can be bypassed by setting −1 bit (Register 0x1B, Bit 6). AD9125 0xFFFF . DACCLK 0 .5 ...
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... AD9125 DAC INPUT CLOCK CONFIGURATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9125 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip phased-locked loop (PLL) that accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency ...
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... Rev Page AD9125 Indication Move to a higher VCO band VCO is operating in the higher end of the frequency band VCO is operating within an optimal region of the frequency band VCO is operating in the lower end of the frequency band ...
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... I I where DACCODE = Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9125 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include ⎞ ...
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... Figure 71. IMD vs. Common-Mode Output Voltage (f AUXILIARY DAC OPERATION The AD9125 has two auxiliary DACs; one is associated with the I path, and the other is associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the output of the associated transmit DAC ...
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... BQP 50Ω 58 IOUT2P Figure 73. Typical Interface Circuitry Between the AD9125 and the ADL537x Family of Modulators BASEBAND FILTER IMPLEMENTATION Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal-level setting resistor across the modulator input ...
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... PLL is typically 80 mA when enabled. Figure 76 through Figure 80 detail the power dissipation of the AD9125 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or analog output frequency ...
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... DATA Figure 80. DVDD18 Power Dissipation vs. f TEMPERATURE SENSOR The AD9125 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed through Register 0x49 and Register 0x4A. The temperature of the die can be calculated by T where T accuracy is ±5 Estimates of the ambient temperature can be made if the power dissipation of the device is known ...
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... FIFO, and a particular clock edge of the system clock. The AD9125 has provisions for enabling multiple devices to be synchronized to each other system clock. The AD9125 supports synchronization in two modes: data rate mode and FIFO rate mode ...
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... AD9125 REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) DCI(2) FRAME(2) SAMPLE RATE CLOCK SYNC CLOCK FPGA Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock t SKEW t t SU_DCI H_DCI Figure 82. Timing Diagram Required for Synchronizing Devices DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAME DCI LOW SKEW ...
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... SKEW t t SU_SYNC H_SYNC t t SU_DCI H_DCI DCI2(2) Figure 84. Data Rate Synchronization Signal Timing Requirements, 2× Interpolation Rev Page each other. A SKEW OUTDLY = ½ × The REFCLK input is DCI CLK DATA Minimum Hold Time, t SU_DCI (ns) 0.59 AD9125 H_DCI ...
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... AD9125 FIFO RATE MODE SYNCHRONIZATION The Procedure for FIFO Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the REFCLK and DACCLK signals are applied to all of the devices. The procedure must be carried out on each individual device ...
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... DCI input and REFCLK. This may allow for more optimal placement of the DCI sampling point in data rate synchronization mode. Table 27. Synchronization Setup and Hold Times Parameter Min t −t SKEW DACCLK t 100 SV_SYNC T 330 H_SYNC Rev Page AD9125 Max Unit / DACCLK ps ps ...
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... AD9125 INTERRUPT REQUEST OPERATION The AD9125 provides an interrupt request output signal (on Pin 7, IRQ ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device ...
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... INTERFACE TIMING VALIDATION The AD9125 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values, which are loaded into registers through the SPI port. Differences between these values are detected and stored ...
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... AD9125 EXAMPLE START-UP ROUTINE There are certain sequences that should be followed to ensure reliable startup of the AD9125. The example start-up routine assumes the following device configuration: • 122.88 MSPS DATA • Interpolation = 4×, using HB1 = 10 and HB2 = 010010 • Input data = baseband data • ...
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... Evaluation Board Connected to ADL5372 Modulator Evaluation Board Connected to ADL5375 Modulator Rev Page 0.60 0.42 0.24 PIN INDICATOR 1 6.15 EXPOSED PAD 6.00 SQ (BOTTOM VIEW) 5. 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-72-7 CP-72-7 AD9125 ...
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... AD9125 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09016-0-6/10(0) Rev Page ...