AD9125 Analog Devices, AD9125 Datasheet - Page 18

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9125
SERIAL PORT OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB-first), the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from the high address to the low address. In
MSB-first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communi-
cation cycle.
When LSB_FIRST = 1 (LSB-first), the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations
if the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x7F for
multibyte I/O operations if the LSB-first mode is active.
Rev. 0 | Page 18 of 56
SCLK
SCLK
SCLK
SCLK
SDIO,
SDIO
SDIO
SDIO
SDO
SDO
SDO
CS
CS
CS
CS
Figure 40. Timing Diagram for Serial Port Register Write (t
Figure 41. Timing Diagram for Serial Port Register Read
R/W A6 A5
Figure 38. Serial Register Interface Timing, MSB First
A0
Figure 39. Serial Register Interface Timing, LSB First
INSTRUCTION CYCLE
INSTRUCTION CYCLE
A1 A2
INSTRUCTION BIT 7
t
t
DS
DS
DATA BIT n
A4 A3
A3 A4
t
PWH
t
t
DH
DV
t
A2 A1
N0 N1 R/W D0
SCLK
t
PWL
INSTRUCTION BIT 6
A0 D7 D6
DATA BIT n – 1
D0
D7 D6
0
0
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
D1
D1
N
N
0
0
D5
D5
D2
D2
N
N
0
0
D4
D3
D4
D3
0
N
N
0
D5
D5
D2
D2
0
N
N
0
DS
D6
D1
D6
D1
to t
N
0
0
N
D7
D7
D0
D0
DCS
N
N
0
0
)