AD9125 Analog Devices, AD9125 Datasheet - Page 19

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

DEVICE CONFIGURATION REGISTER MAP
Table 10. Device Configuration Register Map
Register Name
Comm
Power Control
Data Format
Interrupt Enable 1
Interrupt Enable 2
Event Flag 1
Event Flag 2
Clock Receiver
PLL Control 1
PLL Control 2
PLL Control 3
PLL Status 1
PLL Status 2
Sync Control 1
Sync Control 2
Sync Status 1
Sync Status 2
FIFO Control
FIFO Status 1
FIFO Status 2
Datapath Control
HB1 Control
HB2 Control
HB3 Control
Chip ID
Control
Addr
(Hex)
0x00
0x01
0x03
0x04
0x05
0x06
0x07
0x08
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x17
0x18
0x19
0x1B
0x1C
0x1D
0x1E
0x1F
Bit 7
SDIO
Power-
down
DAC I
Binary
data
format
Enable
PLL lock
lost
0
PLL
lock
lost
DACCLK
duty
correction
PLL
enable
PLL lock
Sync
enable
Sync lost
FIFO
Warning 1
Bypass
premod
PLL loop bandwidth[2:0]
N2[1:0]
Bit 6
LSB_FIRST
Power-
down
DAC Q
Q data
first
Enable
PLL
lock
0
PLL
locked
REFCLK
duty
correction
PLL
manual
enable
Data/FIFO
rate toggle
Sync
locked
FIFO
Warning 2
Bypass
sinc
−1
Bit 5
Reset
Power-
down data
receiver
MSB swap
Enable
sync
signal
lost
0
Sync
signal
lost
DACCLK
cross-
correction
Bypass
NCO
Rev. 0 | Page 19 of 56
Sync phase readback[7:0] (6.2 format)
Bit 4
Power-
down
aux ADC
Enable
sync
signal
lock
Enable
AED
compare
pass
Sync
signal
locked
AED
compare
pass
REFCLK
cross-
correction
PLL cross
control
enable
FIFO level[7:0]
Chip ID[7:0]
HB2[5:0]
HB3[5:0]
Bit 3
Enable
sync
phase
lock
Enable
AED
compare
fail
Sync
phase
locked
AED
compare
fail
1
Rising
edge sync
NCO gain
VCO band readback[5:0]
Sync phase request[5:0]
Manual VCO band[5:0]
PLL charge pump current[4:0]
N0[1:0]
Bit 2
Enable
soft
FIFO
sync
Enable
SED
compare
fail
Soft
FIFO
sync
SED
compare
fail
FIFO soft
align ack
Bypass
phase
compen-
sation and
dc offset
VCO control voltage[3:0]
1
HB1[1:0]
FIFO phase offset[2:0]
Sync Averaging[2:0]
Bit 1
Enable
FIFO
Warning 1
0
FIFO
Warning 1
FIFO soft
align
request
Select
sideband
Data bus width[1:0]
1
N1[1:0]
Bit 0
PLL lock
status
Enable
FIFO
Warning 2
0
FIFO
Warning 2
FIFO reset
aligned
Send I data
to Q data
Bypass HB1
Bypass HB2
Bypass HB3
1
AD9125
Default
0x00
0x10
0x00
0x00
0x00
N/A
N/A
0x3F
0x40
0xD1
0xD9
0x00
0x00
0x48
0x00
N/A
N/A
0x04
N/A
N/A
0xE4
0x00
0x00
0x00
0x08