AD5663 Analog Devices, AD5663 Datasheet - Page 15

• Manufacturer Part Number: AD5663
• Manufacturer: Analog Devices

Specifications of AD5663

• Resolution (bits): 16bit
• Dac Update Rate: 220kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Table 8. Address Command
A2
0
0
0
0
1
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 30).
POWER-ON RESET
The AD5663 family contains a power-on reset circuit that
controls the output voltage during power-up. The AD5663 DAC
outputs power up to 0 V, the AD5663-1 powers up to midscale,
and the output remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up. Any events on LDAC or CLR
during power-on reset are ignored.
Table 10. 24-Bit Input Shift Register Contents for Software Reset Command
MSB
DB23 to DB22
x
Don’t care
SYNC
SCLK
DIN
A1
0
0
1
1
1
DB23 (MSB)
SYNC HIGH BEFORE 24
X
DB23
INVALID WRITE SEQUENCE:
X
DB21
1
Command bits (C2 to C0)
COMMAND BITS
C2
1
A0
0
1
0
1
C1
TH
C0
DB20
0
FALLING EDGE
ADDRESS (n)
DAC A
DAC B
Reserved
Reserved
All DACs
ADDRESS BITS
A2
DB0
A1
DB19
1
A0
D15
DB18
x
Address bits (A2 to A0)
D14
Figure 29. Input Register Contents
Figure 30. SYNC Interrupt Facility
D13
Rev. 0 | Page 15 of 24
D12
DB17
x
D11
D10
SOFTWARE RESET
The AD5663 contains a software reset function. Command 101
is reserved for the software reset function (see Table 7). The
software reset command contains two reset modes that are
software-programmable by setting Bit DB0 in the control
register.
Table 9 shows how the state of the bit corresponds to the mode
of operation of the device. Table 10 shows the contents of the
input shift register during the software reset mode of operation.
Table 9. Software Reset Modes for the AD5663
DB0
0
1 (Power-On Reset)
DB16
x
D9
VALID WRITE SEQUENCE, OUTPUT UPDATES
D8
DATA BITS
DB23
DB15 to DB1
x
Don’t care
ON THE 24
D7
D6
TH
D5
FALLING EDGE
Registers Reset to 0
DAC register
Input register
DAC register
Input register
LDAC register
Power-down register
D4
DB0
1/0
Determines software reset mode
D3
DB0
D2
D1
DB0 (LSB)
D0
AD5663
LSB