AD5663 Analog Devices, AD5663 Datasheet - Page 7

• Manufacturer Part Number: AD5663
• Manufacturer: Analog Devices

Specifications of AD5663

• Resolution (bits): 16bit
• Dac Update Rate: 220kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

PIN CONFIGURATION AND FUNCTION DESCRIPTION
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
V
V
GND
LDAC
CLR
SYNC
SCLK
DIN
V
V
OUT
OUT
DD
REF
A
B
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part
exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during a write
sequence, the write is aborted.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Reference Voltage Input.
V
V
LDAC
OUT
OUT
GND
CLR
A
B
Figure 3. Pin Configuration
1
2
3
4
5
Rev. 0 | Page 7 of 24
(Not to Scale)
AD5663
TOP VIEW
10
9
8
7
6
V
V
DIN
SCLK
SYNC
REF
DD
AD5663