AD5663 Analog Devices, AD5663 Datasheet - Page 16

• Manufacturer Part Number: AD5663
• Manufacturer: Analog Devices

Specifications of AD5663

• Resolution (bits): 16bit
• Dac Update Rate: 220kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5663
POWER-DOWN MODES
The AD5663 contains four separate modes of operation.
Command 100 is reserved for the power-down function
(see Table 7). These modes are software-programmable by
setting Bit DB5 and Bit DB4 in the control register. Table 11
shows how the state of the bits corresponds to the mode of
operation of the device. Any or all DACs (DAC B and DAC A)
can be powered down to the selected mode by setting the
corresponding two bits (Bit DB1 and Bit DB0) to 1. By
executing the same Command 100, any combination of DACs
can be powered up by setting Bit DB5 and Bit DB4 to normal
operation mode. Again, to select which combination of DAC
channels to power up, set the corresponding two bits (Bit DB1
and Bit DB0) to 1. See Table 12 for contents of the input shift
register during power-down/power-up operation.
The DAC output powers up to the value in the input register
while LDAC is low. If LDAC is high, the DAC output powers up
to the value held in the DAC register before power-down.
When both bits are set to 0, the part works normally with its
normal power consumption of 500 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (100 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. The outputs can either be
connected internally to GND through a 1 kΩ or 100 kΩ register
or left open-circuited (three-state) (see Figure 31).
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down.
Table 12. 24-Bit Input Shift Register Contents of Power-Up/Power-Down Function
MSB
DB23 to
DB22
x
Don’t
care
STRING DAC
RESISTOR
DB21
1
Command bits (C2 to C0)
Figure 31. Output Stage During Power-Down
DB20
0
POWER-DOWN
AMPLIFIER
CIRCUITRY
DB19
0
DB18
x
Address bits (A2 to A0);
don’t care
NETWORK
RESISTOR
DB17
x
V
OUT
DB16
x
Rev. 0 | Page 16 of 24
DB15 to
DB6
x
Don’t
care
The time required to exit power-down is typically 4 μs for
V
Table 11. Power-Down Modes of Operation for the AD5663
DB5
0
0
1
1
LDAC FUNCTION
The AD5663 DAC has double-buffered interfaces consisting of
two banks of registers: input registers and DAC registers. The
input registers are connected directly to the input shift register
and the digital code is transferred to the relevant input register
on completion of a valid write sequence. The DAC registers
contain the digital code used by the resistor strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them. The
double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to one of the input registers individually and then, by bringing
LDAC low when writing to the other DAC input register, all
outputs update simultaneously.
These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been
updated since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with
the contents of the input registers. In the case of the AD5663,
the DAC register updates only if the input register has changed
since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
DD
= 5 V and for V
DB5
PD1
Power-down
mode
0
1
DB4
1
0
DB4
PD0
DD
= 3 V (see Figure 18).
DB3
x
Don’t care
Operating Mode
Normal operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-state
DB2
x
DB1
DAC B
Power down/Power up
channel selection;
set bit to 1 to select
channel
LSB
DB0
DAC A