AD5628 Analog Devices, AD5628 Datasheet - Page 22

• Manufacturer Part Number: AD5628
• Manufacturer: Analog Devices

Specifications of AD5628

• Resolution (bits): 12bit
• Dac Update Rate: 95kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5628/AD5648/AD5668
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
amplifier is capable of driving a load of 2 kΩ in parallel with
200 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 32 and Figure 33. The slew rate
is 1.5 V/μs with a ¼ to ¾ scale settling time of 7 μs.
SERIAL INTERFACE
The AD5628/AD5648/AD5668 have a 3-wire serial interface
( SYNC , SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. At this stage, the SYNC line can be kept
low or be brought high. In either case, it must be brought high
for a minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. SYNC
should be idled low between write sequences for even lower
power operation of the part. As is mentioned previously,
however, SYNC must be brought high again just before the next
write sequence.
for a timing diagram of a typical write sequence.
nd
falling clock edge, the last
DD
. The
Rev. F | Page 22 of 32
Table 8. Command Definitions
C3
0
0
0
0
0
0
0
0
1
1
–
1
Table 9. Address Commands
A3
0
0
0
0
0
0
0
0
1
Command
C2
0
0
0
0
1
1
1
1
0
0
–
1
A2
0
0
0
0
1
1
1
1
1
Address (n)
0
0
1
1
0
0
1
1
0
0
–
1
C1
A1
0
0
1
1
0
0
1
1
1
C0
0
1
0
1
0
1
0
1
0
1
–
1
Description
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
Load LDAC register
Reset (power-on reset)
Set up internal REF register
Reserved
Reserved
Reserved
A0
0
1
0
1
0
1
0
1
1
Selected DAC Channel
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
Data Sheet