AD5628 Analog Devices, AD5628 Datasheet - Page 23

• Manufacturer Part Number: AD5628
• Manufacturer: Analog Devices

Specifications of AD5628

• Resolution (bits): 12bit
• Dac Update Rate: 95kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
INPUT SHIFT REGISTER
The input shift register is 32 bits wide. The first four bits are
don’t cares. The next four bits are the command bits, C3 to C0
(see Table 8), followed by the 4-bit DAC address, A3 to A0 (see
Table 9) and finally the 16-/14-/12-bit data-word. The data-
word comprises the 16-/14-/12-bit input code followed by four,
six, or eight don’t care bits for the AD5668, AD5648, and
AD5628, respectively (see Figure 57 through Figure 59). These
data bits are transferred to the DAC register on the 32
edge of SCLK.
DB31 (MSB)
DB31 (MSB)
DB31 (MSB)
X
X
X
SYNC
SCLK
X
X
X
DIN
X
X
X
SYNC HIGH BEFORE 32ND FALLING EDGE
X
X
X
C3
C3
C3
DB31
INVALID WRITE SEQUENCE:
COMMAND BITS
COMMAND BITS
COMMAND BITS
C2
C2
C2
C1
C1
C1
C0
C0
C0
A3
A3
A3
ADDRESS BITS
ADDRESS BITS
ADDRESS BITS
A2
A2
A2
DB0
A1
A1
A1
A0
A0
A0
Figure 57. AD5668 Input Register Contents
Figure 58. AD5648 Input Register Contents
Figure 59. AD5628 Input Register Contents
D15 D14 D13 D12 D11 D10
D11 D10
D13 D12 D11 D10
nd
Figure 60. SYNC Interrupt Facility
falling
Rev. F | Page 23 of 32
D9
D8
D9
D7
DATA BITS
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
32 falling edges of SCLK, and the DAC is updated on the 32
falling edge and rising edge of SYNC . However, if SYNC is brought
high before the 32
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see
D6
D8
DATA BITS
VALID WRITE SEQUENCE, OUTPUT UPDATES
D9
D7
D5
D8
D6
D4
DATA BITS
DB31
ON THE 32ND FALLING EDGE
D7
D5
D3
D6
D4
D2
nd
falling edge, this acts as an interrupt to the
D5
D3
D1
AD5628/AD5648/AD5668
D4
D2
D0
D3
D1
DB0
X
D2
D0
X
D1
X
X
D0
X
X
X
X
X
Figure 60
X
X
X
DB0 (LSB)
DB0 (LSB)
DB0 (LSB)
X
X
X
).
nd
X
X
X