AD5384 Analog Devices, AD5384 Datasheet - Page 12

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5384
I
DV
unless otherwise noted.
Table 8.
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
1
2
3
4
5
6
7
8
9
10
11
2
See
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
falling edge.
C
SCL
b
2
SDA
C SERIAL INTERFACE
SCL
b
is the total capacitance, in pF, of one bus line. t
DD
Figure 6
= 2.7 V to 5.5 V; AV
1
.
t
9
CONDITION
START
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1C
400
t
4
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
b
t
MIN
3
3
, T
MAX
t
R
10
and t
t
6
Figure 6. I
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs m0in
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
F
are measured between 0.3 DV
2
C-Compatible Serial Interface Timing Diagram
t
2
Description
SCL cycle time
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
SCL clock frequency
t
t
t
t
t
t
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
Rev. A | Page 12 of 36
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS-compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS-compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, bus free time between a STOP and a START condition
, SCL low time
, SCL high time
, setup time for repeated start
, start/repeated start condition hold time
, data setup time
, stop condition setup time
, data hold time
, data hold time
t
11
t
5
DD
and 0.7 DV
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
DD
.
CONDITION
REPEATED
START
t
7
t
4
t
MIN
1
to T
MAX
,
CONDITION
STOP
t
8