AD5384 Analog Devices, AD5384 Datasheet - Page 22

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

AD5384
Table 15. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0
11
10
01
00
00
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5384 contains a number of special function registers
(SFRs), as outlined in Table 16. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0.
Table 16. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
X
0
0
0
0
0
1
0
0
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A5–A0 = 000000
Performs no operation but is useful in serial readback mode to
clock out data on D
low during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A5–A0 = 000001
DB13–DB0 = Contain the CLR data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data contained
in the user-configurable CLR register, and sets VOUT0 to
VOUT39, accordingly. This can be very useful for setting up a
specific output voltage in a clear condition. It is also beneficial
for calibration purposes; the user can load full scale or zero
scale to the clear code register and then issue a hardware or
software clear to load this code to all DACs, removing the need
for individual writes to each DAC. Default on power-up is all 0s.
1111
1111
1111
1111
0000
0
0
0
0
0
A5
0
0
0
0
A4
0
0
0
0
0
0
0
0
0
1111
1111
1111
1111
0000
A3
0
0
0
1
1
1
1
1
1
OUT
for diagnostic purposes. BUSY pulses
A2
0
0
0
0
0
1
1
0
1
A1
0
0
1
0
0
0
0
1
1
1110
1110
1110
1110
0000
A0
0
1
0
0
1
0
0
0
1
Function
NOP (No Operation)
Write CLR Code
Soft CLR
Soft Power-Down
Soft Power-Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
Gain Factor
1
0.75
0.5
0.25
0
Rev. A | Page 22 of 36
Soft CLR
REG1 = REG0 = 0, A5–A0 = 000010
DB13–DB0 = Don’t Care
Executing this instruction performs the CLR, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code
register. It takes 35 µs to fully execute the SOFT CLR, as
indicated by the BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A5–A0 = 001000
DB13–DB0 = Don’t Care
Executing this instruction performs a global power-down that
puts all channels into a low power mode that reduces the analog
supply current to 2 µA maximum and the digital current to
20 µA maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 kΩ load to ground. The contents of all internal registers are
retained in power-down mode. No register can be written to
while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A5–A0 = 001001
DB13–DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 µs. The
hardware power-down and software function are internally
combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A5–A0 = 001111
DB13–DB0 = Don’t Care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 µs.