AD5384 Analog Devices, AD5384 Datasheet - Page 21

• Manufacturer Part Number: AD5384
• Description: 40-Channel, 3 V/5 V Single Supply,14-Bit, Serial Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5384

• Resolution (bits): 14bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser,SPI

FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5384 is a complete single-supply, 40-channel, voltage
output DAC offering 14-bit resolution, available in a 100-lead
CSPBGA package. It features two serial interfaces, SPI and I
This family includes an internal1.25/2.5 V, 10 ppm/°C
reference that can be used to drive the buffered reference
inputs. Alternatively, an external reference can be used to drive
these inputs. Reference selection is via a bit in the control
register. Internal/external reference selection is via the CR10 bit
in the control register; CR12 selects the reference magnitude if
the internal reference is selected. All channels have an on-chip
output amplifier with rail-to-rail output capable of driving 5 kΩ
in parallel with a 200 pF load.
INPUT DATA
The architecture of a single DAC channel consists of a14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 14-bitbinary digital code
loaded to the DAC register determines at which node on the
string the voltage is tapped off before being fed to the output
amplifier.
Each channel on these devices contains independent offset and
gain control registers allowing the user to digitally trim offset
and gain. These registers let the user calibrate out errors in the
complete signal chain including the DAC using the internal m
and c registers which hold the correction factors. All channels
are double buffered allowing synchronous updating of all
channels using the LDAC pin. Figure 26 shows a block diagram
of a single channel on the AD5384. The digital input transfer
function for each DAC can be represented as
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5384).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and the LSB (DB0) is 0.
n is the DAC resolution (n = 14 for AD5384).
c is the14-bit offset coefficient (default is 0x2000).
x2 = [(m + 2)/ 2
×1 INPUT
m REG
c REG
REG
Figure 26. Single-Channel Architecture
AGND
×2
V
n
14-BIT
REF
× x1] + (c – 2
DAC
(+)
AVDD
n – 1
)
R
R
V
OUT
2
Rev. A | Page 21 of 36
C.
The complete transfer function for these devices can be
represented as
where:
x2 is the data-word loaded to the resistor string DAC.
V
externally applied to the DAC REFOUT/REFIN pin. For
specified performance, an external reference voltage of 2.5 V is
recommended for the AD5384-5, and 1.25 V for the AD5384-3.
DATA DECODING
The AD5384 contains a 14-bit data bus, DB13-DB0. Depending
on the value of REG1 and REG0 outlined in Table 12, this data
is loaded into the addressed DAC input register(s), offset (c)
register(s), or gain (m) register(s). The format data, offset (c)
and gain (m) register contents are outlined in Table 13, Table 14,
and Table 15.
Table 12. Register Selection
REG1
1
1
0
0
Table 13. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0
11
11
10
10
01
00
00
Table 14. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0
11
11
10
10
01
00
00
REF
is the internal reference voltage or the reference voltage
V
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
OUT
= 2 × V
REG0
1
0
1
0
1111
1111
0000
0000
1111
0000
0000
1111
1111
0000
0000
1111
0000
0000
REF
× x2/2
Register Selected
Input Data Register (x1)
Offset Register (c)
Gain Register (m)
Special Function Registers (SFRs)
1111
1110
0001
0000
1111
0001
0000
1111
1110
0001
0000
1111
0001
0000
n
DAC Output (V)
2 V
2 V
2 V
2 V
2 V
2 V
0
REF
REF
REF
REF
REF
REF
Offset (LSB)
+8191
+8190
+1
0
–1
–8191
–8192
× (16383/16384)
× (16382/16384)
× (8193/16384)
× (8192/16384)
× (8191/16384)
× (1/16384)
AD5384