AD5305 Analog Devices, AD5305 Datasheet - Page 5

• Manufacturer Part Number: AD5305
• Manufacturer: Analog Devices

Specifications of AD5305

• Resolution (bits): 8bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: I2C/Ser 2-wire,Ser

AC CHARACTERISTICS
V
Table 2.
Parameter
Output Voltage Settling Time
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1
2
3
TIMING CHARACTERISTICS
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
SCL
1
2
3
4
5
6
7
8
9
10
11
Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization, not production tested.
See the Terminology section.
See Figure 2.
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
falling edge.
C
B
3
DD
DD
4
B
AD5305
AD5315
AD5325
is the total capacitance of one bus line in pF. t
= 2.5 V to 5.5 V, R
= 2.5 V to 5.5 V, all specifications T
2, 3
1, 2
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 C
400
L
= 2 kΩ to GND, C
MIN
B
4
, T
MAX
(A, B Version)
MIN
R
and t
L
to T
= 200 pF to GND, all specifications T
F
Min
measured between 0.3 V
MAX
, unless otherwise noted.
A, B Version
1
Typ
6
7
8
0.7
12
1
3
200
−70
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Rev. G | Page 5 of 24
Max
8
9
10
1
DD
Conditions/Comments
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
and 0.7 V
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, bus-free time between a stop and a start condition
, SCL low time
, SCL high time
Unit
μs
μs
μs
V/μs
nV-s
nV-s
nV-s
nV-s
kHz
dB
, setup time for repeated start
, stop condition setup time
, start/repeated start condition hold time
, data setup time
, data hold time
, data hold time
IH
DD
min of the SCL signal) in order to bridge the undefined region of SCL’s
.
MIN
Conditions/Comments
V
¼ scale to ¾ scale change (0×40 to 0×C0)
¼ scale to ¾ scale change (0×100 to 0×300)
¼ scale to ¾ scale change (0×400 to 0×C00)
1 LSB change around major carry
V
V
REF
REF
REF
to T
= V
= 2 V ± 0.1 V p-p
= 2.5 V ± 0.1 V p-p, frequency = 10 kHz
DD
MAX
= 5 V
, unless otherwise noted.
AD5305/AD5315/AD5325