AD9752 Analog Devices, AD9752 Datasheet

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AD9752

Manufacturer Part Number
AD9752
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD9752

Resolution (bits)
12bit
Dac Update Rate
125MSPS
Dac Settling Time
35ns
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Par

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a
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT DESCRIPTION
The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC family,
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.
The AD9752’s flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.
The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.
REV. 0
5703519.
FEATURES
High Performance Member of Pin-Compatible
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 79 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct Digital Synthesis (DDS)
Instrumentation
TxDAC Product Family
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
12-Bit, 125 MSPS High Performance
The AD9752 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 k output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9752 is a member of the wideband TxDAC product
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
2. Manufactured on a CMOS process, the AD9752 uses a
3. On-chip, edge-triggered input CMOS latches interface readily
4. A flexible single-supply operating range of 4.5 V to 5.5 V and
5. The current output(s) of the AD9752 can be easily config-
family that provides an upward or downward component selec-
tion path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9752 to operate at reduced power levels.
ured for various single-ended or differential circuit topologies.
CLOCK
R
SET
0.1 F
+5V
FUNCTIONAL BLOCK DIAGRAM
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
+1.20V REF
TxDAC
World Wide Web Site: http://www.analog.com
REFLO
DIGITAL DATA INPUTS (DB11–DB0)
SEGMENTED
SWITCHES
®
150pF
LATCHES
D/A Converter
CURRENT
© Analog Devices, Inc., 1999
SOURCE
SWITCHES
ARRAY
LSB
+5V
AD9752*
AVDD
AD9752
ACOM
IOUTA
IOUTB
ICOMP
0.1 F

Related parts for AD9752

AD9752 Summary of contents

Page 1

... BiCMOS devices. 3. On-chip, edge-triggered input CMOS latches interface readily to +2 CMOS logic families. The AD9752 can support update rates up to 125 MSPS flexible single-supply operating range of 4 5.5 V and a wide full-scale current adjustment span allow the AD9752 to operate at reduced power levels ...

Page 2

... AD9752–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + MIN MAX Differential Nonlinearity (DNL + MIN MAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current ...

Page 3

... AD9752 Units MSPS pA/ Hz pA/ Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...

Page 4

... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9752 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 5

... DCOM 4 DB8 25 NC DB7 5 24 AVDD AD9752 DB6 6 23 ICOMP TOP VIEW (Not to Scale) DB5 7 22 IOUTA DB4 8 21 IOUTB DB3 9 ACOM 20 DB2 DB1 ADJ 12 DB0 17 REFIO REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9752 ...

Page 6

... T . For MIN MAX +5V REFLO AVDD ACOM 150pF AD9752 PMOS ICOMP CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB FOR DB11–DB3 SWITCHES LATCHES ...

Page 7

... A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9752 = +25 C, SFDR up to Nyquist, unless otherwise noted 0dBFS –6dBFS 70 60 –12dBFS – MHz OUT Figure 5. SFDR vs. f ...

Page 8

... AD9752 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 0 1000 2000 3000 4000 CODE Figure 12. Typical INL 125MSPS CLK – 13.5MHz OUT1 – 14.5MHz OUT2 A = 0dBFS OUT –30 SFDR = 68.4dBc –40 –50 –60 –70 –80 –90 –100 – MHz OUT Figure 15 ...

Page 9

... CLOCK FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9752. The AD9752 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...

Page 10

... Figure 19. External Reference Configuration AVDD 1.2V AD1580 REFERENCE CONTROL AMPLIFIER The AD9752 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a V-I converter as shown in Figure 19, such that its current output, I the ratio of the V in Equation 4 ...

Page 11

... V is set by the breakdown limits of the CMOS process. SET Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9752 The positive output compliance range is slightly dependent on GC the full-scale output current not exceed 62 ...

Page 12

... The drivers of the digital data interface circuitry should be specified to meet the mini- mum setup and hold times of the AD9752 as well as its re- quired min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above con- ditions will result in the lowest data feedthrough and noise ...

Page 13

... SLEEP MODE OPERATION The AD9752 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also con- tains an active pull-down circuit that ensures the AD9752 re- mains enabled if this input is left disconnected ...

Page 14

... In this case, AVDD which is the positive analog supply for both the AD9752 and the op amp is also used to level-shift the differ- ential output of the AD9752 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...

Page 15

... PSRR of the DAC at 1 MHz which Figure 33 becomes Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9752 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system ...

Page 16

... MHz which is represented in Figure 35b. In both cases, the spurious free range between the transmitted tones and the empty bins is greater than 60 dB. Using the AD9752 for Quadrature Amplitude Modulation (QAM) QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i ...

Page 17

... DAC. The differential voltage outputs of U1 and U2 are fed into the respective differential inputs of the AD8346 via matching networks. Using the same matching techniques described above, Figure 38 shows an example of the AD9752 used in a W-CDMA transmit- ter application using the AD6122 CDMA 3 V transmitter IF REFLO REFIO AD9752 (“ ...

Page 18

... AD9752 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9752 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs ...

Page 19

... REV. 0 Figure 41. Evaluation Board Schematic –19– AD9752 ...

Page 20

... AD9752 Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) –20– REV. 0 ...

Page 21

... REV. 0 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –21– AD9752 ...

Page 22

... AD9752 Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom –22– REV. 0 ...

Page 23

... PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) SEATING 0.0125 (0.32) (1.27) 0.0138 (0.35) PLANE BSC 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –23– AD9752 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40) 0.028 (0.70 0.020 (0.50) ...

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