AD9752 Analog Devices, AD9752 Datasheet - Page 11

• Manufacturer Part Number: AD9752
• Manufacturer: Analog Devices

Specifications of AD9752

• Resolution (bits): 12bit
• Dac Update Rate: 125MSPS
• Dac Settling Time: 35ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
varied by an external voltage, V
fier. An example of this method is shown in Figure 21, in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
referenced to ACOM and should not exceed 1.2 V. The value
of R
and 625 A, respectively. The associated equations in Figure 21
can be used to determine the value of R
ANALOG OUTPUTS
The AD9752 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V
V
Transfer Function section by Equations 5 through 8. The
differential voltage, V
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 22 shows the equivalent analog output circuit of the
AD9752 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 k in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I
signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.
REV. 0
OUTB
SET
, via a load resistor, R
V
1 F
is such that I
Figure 21. Dual-Supply Gain Control Circuit
GC
Figure 22. Equivalent Analog Output
R
SET
OUTFS
REFMAX
I
I
WITH V
DIFF
REF
REF
. Although the output impedance’s
= (1.2–V
, existing between V
GC
REFIO
FS ADJ
AD9752
+1.2V REF
and I
< V
LOAD
GC
REFIO
GC
REFLO
)/R
IOUTA
REFMIN
R
, applied to R
, as described in the DAC
SET
LOAD
AND 62.5 A
150pF
SET
do not exceed 62.5 A
.
AVDD
R
OUTA
IOUTB
LOAD
I
CURRENT
OUTA
REF
SET
SOURCE
ARRAY
AVDD
AVDD
and V
via an ampli-
625A
and V
OUTA
OUTB
REF
GC
OUTB
and
, is
is
)
–11–
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9752.
The positive output compliance range is slightly dependent on
the full-scale output current, I
nominal 1.25 V for an I
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9752’s linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9752
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9752 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of 4.5 V to 5.5 V.
Operating the AD9752 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from –1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9752 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
R
examples of various output configurations.
The most significant improvement in the AD9752’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both
IOUTA and IOUTB can be substantially reduced by the
common-mode rejection of a transformer or differential am-
plifier. These common-mode error sources include even-
order distortion products and noise. The enhancement in
distortion performance becomes more significant as the recon-
structed waveform’s frequency content increases and/or its
amplitude decreases.
The distortion and noise performance of the AD9752 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, I
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance. Although I
20 mA, selecting an I
tortion and noise performance also shown in Figure 8. The
noise performance of the AD9752 is affected by the digital sup-
ply (DVDD), output frequency, and increases with increasing
clock rate as shown in Figure 11. Operating the AD9752 with
low voltage logic levels between 3 V and 3.3 V will slightly re-
duce the amount of on-chip digital noise.
LOAD
accordingly. Refer to Applying the AD9752 section for
OUTFS
OUTFS
OUTFS
OUTFS
of 20 mA will provide the best dis-
= 20 mA to 1.00 V for an I
OUTFS
. Operating the analog supply at
can be set between 2 mA and
. It degrades slightly from its
AD9752
OUTFS
=