AD768 Analog Devices, AD768 Datasheet - Page 8

• Manufacturer Part Number: AD768
• Description: 16-Bit, 30 MSPS D/A Converter
• Manufacturer: Analog Devices

Specifications of AD768

• Resolution (bits): 16bit
• Dac Update Rate: 30MSPS
• Dac Settling Time: 25ns
• Max Pos Supply (v): +5.25V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD768
The outputs have a compliance range of –1.2 V to +5.0 V with
respect to LADCOM. The current steering output stages will
remain functional over this range. Operation beyond the maxi-
mum compliance limits may cause either output stage saturation
or breakdown, resulting in nonlinear performance. The rated dc
and ac performance specifications are for an output voltage of
0 V to –1 V.
The current in LADCOM is proportional to I
carefully configured to be independent of digital code when the
output is connected to a virtual ground. This minimizes any det-
rimental effects of ladder ground resistance on linearity. For
optimal dc linearity, IOUTA should be connected directly to a
virtual ground, and IOUTB should be grounded. An example of
this configuration is provided in the section “Buffered Voltage
Output.” If IOUTA is driving a resistive load directly, then
IOUTB should be terminated with an equal impedance. This
will ensure the current in LADCOM remains constant with digi-
tal code, and is recommended for improved dc linearity in the
unbuffered voltage output configuration.
As shown in Figure 10, there is an equivalent output impedance
of 1 k in parallel with 3 pF at each output terminal. If the out-
put voltage deviates from the ladder common voltage, an error
current flows through this 1 k impedance. This is a linear effect
which does not change with input code, so it appears as a gain
error. With 50
approximately –5%. An example of this configuration is pro-
vided in the section Unbuffered Voltage Output.
–2
–4
–6
–8
8
6
4
2
0
0
Figure 9. Typical DNL Performance
5
output termination, the resulting gain error is
10
15
20
DIGITAL INPUT CODE – k
25
30
35
40
45
50
REFIN
55
and has been
60
65
–8–
DIGITAL INPUTS
The AD768 digital inputs consist of 16 data input pins and a
clock pin. The 16-bit parallel data inputs follow standard posi-
tive binary coding, where DB15 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA pro-
duces full-scale output current when all data bits are at logic 1.
IOUTB is the complementary output, with full-scale when all
data bits are at logic 0. The full-scale current is split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock, and is designed to support a clock rate
as high as 40 MSPS. The clock can be operated at any duty
cycle that meets the specified minimum latch pulse width. The
setup and hold times can also be varied within the clock cycle as
long as the specified minimums are met, although the location
of these transition edges may affect digital feedthrough. The
digital inputs are CMOS compatible with logic thresholds set to
approximately half the positive supply voltage. The small input
current requirements allow for easy interfacing to unbuffered
CMOS logic. Figure 11 shows the equivalent digital input
circuit.
Digital input signals to the DAC should be isolated from the
analog output as much as possible. Interconnect distances to the
DAC inputs should be kept as short as possible. Termination
resistors may improve performance if the digital lines become
too long. To minimize digital feedthrough, the inputs should be
free from glitches and ringing, and may be further improved
with a reduction of edge speed.
Figure 10. Equivalent Analog Output Circuit
Figure 11. Equivalent Digital Input Circuit
I
OUT
DIGITAL
IOUTA
INPUT
1
1k
3pF
V
V
LADCOM
CC
EE
V
28
26
EE
IREFIN
x2.75
1k
3pF
IOUTB
DCOM
V
27
CC
I
OUT
REV. B