STA120D STMicroelectronics, STA120D Datasheet - Page 10

• Manufacturer Part Number: STA120D
• Description: IC RECEIVER AUDIO DIGITAL 28SOIC
• Manufacturer: STMicroelectronics
• Type: Digital Audio Interface Receiverr

Specifications of STA120D

• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 497-3942-5; 497-3942-5; 497-3943-5

STA120
The validity flag indicates that the validity bit for a previous sample was high since the last clearing of the
error codes. The slipped sample error can only occur when FSYNC and SCK of the audio serial port are
inputs. In this case, if FSYNC is asynchronous to the received data rate, periodically a stereo sample will
be dropped or reread depending on whether the read rate is slower or faster than the received data rate .
When this occurs, the slipped sample error code will appear on the "E" pins.
The CRC error is updated at the beginning of a channel status block, and is only valid when the profes-
sional format of channel status data is received. This error is indicated when the STA120 calculated CRC
value does not match the CRC byte of the channel status block or when a block boundary changes (as in
removing samples while editing).
The parity error occurs when the incoming sub-frame does not have even parity as specified by the stan-
dards. The biphase coding error indicates a biphase coding violation occurred. The no lock error indicates
that the PLL is not locked onto the incoming data stream. Lock is achieved after receiving three frame pre-
ambles then one block preamble, and is lost after not receiving four consecutive frame preambles.
The receive frequency information is encoded on pins F2, F1 and F0, and is decoded as shown in Table
6. The on-chip frequency comparator compares the received clock frequency to an externally supplied
6.144MHz clock which is input on the FCK pin. The "F" pins. The clock on FCK must be valid for two thirds
of a block for the "F" pins to be accurate.
Table 4. Sample Frequency Decoding
Channel Status Reporting
When SEL is high, channel status is displayed on C0, and Ca-Ce for the channel selected by CS12. If
CS12 is low, channel status for sub-frame1 is displayed, and if CS12 is high, channel status for subframe
2 is displayed. the contents of Ca-Ce depend upon the C0 professional/consumer bit. The information re-
port is shown in Table 5.
Table 5. Channel Status Pins
10/15
F2
0
0
0
0
1
1
1
1
Pin
C0
Ca
Cb
Cd
Ce
Cc
F1
0
0
1
1
0
0
1
1
F0
0
1
0
1
0
1
0
1
Out of Range
48KHz ±4%
44.1KHz ±4%
32KHz ±4%
48KHz ±400ppm
44.1KHz ±400ppm
44.056KHz ±400ppm
32KHz ±400ppm
Professional
0 (low)
CRCE
EM0
EM1
C1
C9
Error
Consumer
1 (high)
IGCAT
ORIG
C1
C2
C3