STA120D STMicroelectronics, STA120D Datasheet - Page 4

• Manufacturer Part Number: STA120D
• Description: IC RECEIVER AUDIO DIGITAL 28SOIC
• Manufacturer: STMicroelectronics
• Type: Digital Audio Interface Receiverr

Specifications of STA120D

• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Other names: 497-3942-5; 497-3942-5; 497-3943-5

PINS DESCRIPTION (continued)
STA120
DIGITAL CHARACTERISTICS (T
Note 1: FS is defined as the incoming audio sample frequency per channel.
SWITCHING CHARACTERISTICS - SERIAL PORTS (T
Note 2: The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio
4/15
Receiver Interface
Phase Locked Loop
Symbol
Symbol
V
I
dd_DYN
I
D+
MCK
dd_ST
V
V
f
16
27
28
10
19
20
25
V
N.
V
F
sck
9
I
OH
t
OL
in
,V
IH
IL
S
j
samples). Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode 32 SCK periods must
be provided in most serial port formats.
A+
SCK Frequency
Power supply voltage Range
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
Input Sample Frequency
Master Clock frequency
MCK Clock Jitter
MCK Duty Cycle
Static I
Dynamic Idd
Name
VERF
MCK
RXP
RXN
ERF
SEL
FILT
Ce
F2
dd
(MCK = 0)
Parameter
Select.Control pin that selects either channel status information (SEL = 1) or error and frequency
information (SEL = 0) to be displayed on six (C0, Ca Cb, Cc, Cd, Ce) pins.
Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is
high. Channel status information is displayed for the channel selected by CS12. C0, which is
channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further
controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL.
Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL
low. A proper clock on FCK must be input for at least two thirds of a channel status block for
these pins to be valid. They are updated three times per block, starting at the block boundary.
Validity + Error Flag. A logical OR'ing of the validity bit from the received data and the error flag.
May be used by interpolation filters to interpolate through errors.
Line Receiver. (RS422 compatible)
Line Receiver. (RS422 compatible)
Master Clock.Low Jitter clock output of 256 times the received sample frequency.
Filter.An external 330 Ohm resistor and 0.47 F capacitor in parallel with a 15nF capacitor is
required from FILT pin to analog ground.
Error Flag,Signals that an error has occurred while receiving the audio sample currently being
read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation
during the current sample, or an out of lock PLL receiver.
Parameter
amb
= 25°C; V
(Note 2)
I
(Note 1)
I
(Note 1)
(high time/cycle time)
O
O
= 200 A
= 3.2mA
Test Condition
D+
Test Condition
, V
A+
= 3.3V ±10%)
Description
amb
= 25°C; V
D+
Min.
, V
V
Min.
DD
3.0
2.0
6.4
25
A+
-1.0
= 3.3V ±10%)
OWRx32
Typ.
256xFS
Typ.
300
3.3
1.0
0.1
50
6
Max.
Max.
+0.8
3.6
0.4
10
96
25
15
1
ps RMS
MHz
Unit
Unit
kHz
mA
mA
Hz
%
V
V
V
V
V
A