CLC5903VLA/NOPB National Semiconductor, CLC5903VLA/NOPB Datasheet - Page 25

• Manufacturer Part Number: CLC5903VLA/NOPB
• Description: IC DGTL TUNER/AGC DUAL 128-PQFP
• Manufacturer: National Semiconductor
• Type: Tunerr

Specifications of CLC5903VLA/NOPB

• Applications: Base Stations
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *CLC5903VLA; *CLC5903VLA/NOPB; CLC5903VLA

leading ‘1’ out of the CIC filter. An output of ‘001XX’ corre-
sponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent
increases by one each time the leading ‘1’ advances in bit
position. The mantissa bits are the two bits that follow the
leading ‘1’. If we define E as the decimal value of the expo-
nent bits and M as the decimal value of the mantissa bits, the
output of the CIC filter, P
“FIXED TO FLOAT CONVERTER” output is,
The max() and min() operators account for row 1 of Table 3
which is a special case because M=P
ates each address of the RAM with a CIC filter output.
As shown in Figure 34, the 32X8 RAM look-up table imple-
ments the functions of log converter, reference subtraction,
error amplifier, and deadband. The user must build each of
these functions by constructing a set of 8-bit, 2’s complement
numbers to be loaded into the RAM. Each of these functions
and how to construct them are discussed in the following
paragraphs.
A log conversion is done in order to keep the loop gain inde-
pendent of operating point. To see why this is beneficial, the
control gain of the DVGA computed without log conversion is,
where G is the decimal equivalent of GAIN and G
for the DVGA gain in excess of unity. This equation assumes
that the DVGA gain control polarity is positive as is the case
for the CLC5526. The gain around the entire loop must be
negative. Observe in Equation 6 that the control gain is
dependent on operating point G. If we instead compute the
control gain with log conversion,
which is no longer operating-point dependent. The log func-
tion is constructed by computing the CIC filter output associ-
ated with each address (Equation 5) and converting these to
dB. Full scale (dc signal) is
AGC Theory of Operation
Table 3. Fixed to Float Converter Truth Table
P
OUT
K
128-255
256-511
INPUT
DVGA
64-127
16-31
32-63
8-15
K
0-3
4-7
DVGA
=
2
4 min E 1
=
=
max E 1
–
=
=
G
6.02,
–
20
v
G
,
i
,
20
OUT
v
ln
–
log
i
1
log
2
2
, corresponding to a given
+
,
v
E
G G
M
i
511
–
2
2
1.
OUT
G G
o
G G
–
=
–
OUTPUT
(eeemm)
,
. Equation 5 associ-
54dB
000XX
001XX
010XX
011XX
100XX
101XX
110XX
111XX
o
(Continued)
o
,
,
.
o
accounts
(5)
(6)
(7)
25
The reference subtraction is constructed by subtracting the
desired loop servo point (in dB) from the table values com-
puted in the previous paragraph. For example, if it is desired
that the DVGA servo the ADC input level (sinusoidal signal)
to -6dBFS, the number to subtract from the data is
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider than
6dB should then be constructed symmetrically about this
point. This prevents the loop from hunting due to the 6dB
gain steps of the DVGA. Any deadband in excess of 6dB
appears as hysteresis in the servo point of the loop as illus-
trated in Figure 33. The deadband is constructed by loading
zeros into those addresses on either side of the one which
corresponds to the reference level.
The last function of the RAM table is that of error amplifica-
tion. All the operations preceding this one gave a table slope
time constant of the loop given by,
The term G
The design equations are obtained by solving Equation 9 for
G
trol register value that determines the number of bits to shift
the output of the RAM down by. This allows some of the loop
gain to be moved out of the RAM so that the full output range
of the table is utilized but not exceeded. The valid range for
AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 1 to
4 bit shift left.
An example set of numbers to implement a loop having a ref-
erence of 6dB below full scale, a deadband of 8dB, and a
loop gain of 0.108 is:
These values are shown plotted in Figure 37 with respect to
the table addresses in (a), and the CIC filter output P
(b). For a 52MHz clock rate and AGC_LOOP_GAIN=2, these
values result in a loop time constant of
The error signal from the loop gain “SHIFT DOWN” circuit is
gated into the loop integrator. The gate is controlled by a tim-
ing and control circuit discussed in the next paragraph. A
MUX within the integrator feedback allows the integrator to
be initialized to the value loaded into AGC_IC_A (channel B
can be set independently). The conditions under which it is
initialized are configured in the registers associated with the
timing and control circuit. The top eight bits of the integrator
output can also be read back over the microprocessor inter-
face from the AGC_RB_A (or AGC_RB_B) register. The top
3 bits below the sign become AGAIN and are output along
with ASTROBE signal on the DVGA interface pins. The valid
range of AGAIN is from 0 to 7 which corresponds to a valid
range of 0 to 2
output from which AGAIN is derived. This is illustrated in Fig-
S
L
RAM
and Equation 10 for
=
G
L
1
=
-102 -102 -88 -80 -75 -70 -66
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
-22 -19 -15 -11
0
. This must now be adjusted in order to control the
L
–
in this equation is the loop gain,
6.02 S
0
10
20
-1 for the 11-bit, 2’s complement integrator
0
log
RAM
=
0


511
--------- -
---------- -
F
S
2
8
CK
RAM
0
2


2
-- -
AGC_LOOP_GAIN 8
------ -
G
0
1
13


. AGC_LOOP_GAIN is a con-
L
=
+
44dB
1
-- -
2
17
 .

1.5 s
20
.
–
.
www.national.com
.
OUT
(10)
(8)
(9)
in