LPC1112FD20 NXP Semiconductors, LPC1112FD20 Datasheet - Page 51

The LPC1112FD20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/1

LPC1112FD20

Manufacturer Part Number
LPC1112FD20
Description
The LPC1112FD20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/1
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC111X
Product data sheet
CAUTION
7.17.5 APB interface
7.17.6 AHBLite
7.17.7 External interrupt inputs
7.18 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 1 March 2012
Section
LPC1110/11/12/13/14/15
7.17.1).
32-bit ARM Cortex-M0 microcontroller
© NXP B.V. 2012. All rights reserved.
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