LPC1112FD20 NXP Semiconductors, LPC1112FD20 Datasheet - Page 61

The LPC1112FD20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/1

LPC1112FD20

Manufacturer Part Number
LPC1112FD20
Description
The LPC1112FD20 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/1
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
LPC111X
Product data sheet
Fig 17. Active mode: Typical supply current I
Fig 18. Sleep mode: Typical supply current I
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(mA)
(mA)
I
I
DD
DD
12
Conditions: V
disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks
disabled; internal pull-up resistors disabled; BOD disabled.
clock frequencies (for LPC111x/101/201/301)
Conditions: V
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
clock frequencies (for LPC111x/101/201/301)
8
4
0
8
6
4
2
0
−40
−40
All information provided in this document is subject to legal disclaimers.
DD
DD
= 3.3 V; active mode entered executing code
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
Rev. 7 — 1 March 2012
−15
−15
10
10
LPC1110/11/12/13/14/15
DD
DD
versus temperature for different system
versus temperature for different system
32-bit ARM Cortex-M0 microcontroller
35
35
48 MHz
36 MHz
24 MHz
12 MHz
48 MHz
36 MHz
24 MHz
12 MHz
while(1){}
(2)
(2)
(2)
(1)
(2)
(2)
(2)
(1)
60
60
temperature (°C)
temperature (°C)
from flash; all peripherals
© NXP B.V. 2012. All rights reserved.
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