LH75401_LH75411_N NXP Semiconductors, LH75401_LH75411_N Datasheet - Page 27

• Manufacturer Part Number: LH75401_LH75411_N
• Description: The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices
• Manufacturer: NXP Semiconductors

System-on-Chip
Color LCD Controller (CLCDC)
connects to the AHB. It translates pixel-coded data into
the required formats and timings to drive single/dual
monochrome and color LCD panels. Packets of pixel-
coded data are fed, via the AHB interface, to two inde-
pendently programmable, 32-bit-wide DMA FIFOs.
Each FIFO is 16 words deep by 32 bits wide.
to the Vectored Interrupt Controller (VIC) when an
interrupt condition becomes true for upper/lower panel
DMA FIFO underflow, base address update significa-
tion, vertical compare, or bus error.
NOTE: LH75401 and LH75411 microcontrollers support full-color
CLCDC FEATURES
• STN, Color STN, TFT, HR-TFT, and AD-TFT
• Programmable Resolution
• Single and Dual Panels
• Supports Sharp and non-Sharp Panels
• CLCDC Outputs Available as General Purpose
• Additional Features
• Programmable Panel-related Parameters
Preliminary data sheet
Inputs/Outputs (GPIOs) if LCDC is Not Needed
The CLCDC is an AMBA master-slave module that
The CLCDC generates a single combined interrupt
– Fully Programmable Timing Controls
– Advanced LCD Interface for displays with a low
– Up to VGA (640 × 480 DPI), 12-bit Direct Mode
– Up to SVGA (800 × 600 DPI), 8-bit Direct/Palet-
– Up to XGA (1,024 × 768 DPI), 4-bit Direct Color/
– Direct or Palettized Colors
– Fully programmable horizontal and vertical timing
– 256-entry, 16-bit palette RAM physically arranged
– AC bias signal for STN panels and a data-enable
– STN mono/color or TFT display
– Bits-per-pixel
– STN 4- or 8-bit Interface Mode
– STN Dual or Single Panel Mode
– AC panel bias
– Panel clock frequency
– Number of panel clocks per line
– Signal polarity, active HIGH or LOW
– Little Endian data format
– Interrupt-generation event.
level of integration, such as HR-TFT and AD-TFT
Color
tized Color
Grayscale
for different display panels
as a 128 × 32-bit RAM
signal for TFT panels.
operation.
NXP Semiconductors
Rev. 01 — 16 July 2007
ADVANCED LCD INTERFACE
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The ALI also pro-
vides a bypass mode that allows interfacing to the built-
in timing ASIC in standard TFT and STN panels.
NOTES:
1. The Advanced LCD Interface pertains to the LH75401 and
2. VGA and XGA modes require 66 MHz core speed.
Universal Asynchronous
Receiver Transmitters (UARTs)
three UARTs, designated UART0, UART1, and UART2.
UART 0 AND 1 FEATURES
• Similar functionality to the industry-standard 16C550
• Supported baud rates up to 921,600 baud (given an
• Supported character formats:
• Full-duplex operation
• Separate transmit and receive FIFOs, with:
• Programmable baud-rate generator that:
• DMA support
• Support for generating and detecting breaks during
• Loopback testing.
external crystal frequency of 14.756 MHz)
UART transactions
The Advanced LCD Interface (ALI) allows for direct
LH75411 microcontrollers.
The LH75401/LH75411 microcontrollers incorporate
– Data bits per character: 5, 6, 7, or 8
– Parity generation and detection: Even, odd, stick,
– Stop bit generation: 1 or 2
– Programmable depth (1 to 16)
– Programmable-service ‘trigger levels’ (1/8, 1/4,
– Overrun protection.
– Enables the UART input clock to be divided by 16
– Generates an internal clock common to both
or none
1/2, 3/4, and 7/8)
to 65,535 × 16
transmit and receive portions of the UART.
LH75401/LH75411
27