LH79524_LH79525_N NXP Semiconductors, LH79524_LH79525_N Datasheet - Page 42
LH79524_LH79525_N
Manufacturer Part Number
LH79524_LH79525_N
Description
The LH79524/LH79525, powered by an ARM720T,is a complete System-on-Chip with a high level of integrationto satisfy a wide range of requirements andapplications
Manufacturer
NXP Semiconductors
Datasheet
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LH79524/LH79525
SDRAM MEMORY CONTROLLER WAVEFORMS
SDRAM Burst Read (page already open). Figure 22
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
42
Figure 21 shows the waveform and timing for an
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. SDCKE is HIGH.
SDRAMcmd
D[31:0]
A[14:0]
DQMx
SCLK
t SDCLK
Figure 21. SDRAM Burst Read
NXP Semiconductors
t OVXXX
Rev. 01 — 16 July 2007
t OVDQ
READ
COLUMN
BANK,
t OHXXX
t OVA
LATENCY = 2
NOP
CAS
tISD tIHD
NOP
DATA n
NOP
t OHDQ
DATA n + 1
READ
DATA n + 2
NOP
DATA n + 3
Preliminary data sheet
NOP
System-on-Chip
LH79525-3
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