LPC3180 NXP Semiconductors, LPC3180 Datasheet - Page 25

• Manufacturer Part Number: LPC3180
• Description: The LPC3180 is an ARM9-based microcontroller for embedded applications requiringhigh performance combined with low power dissipation
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3180_2
Preliminary data sheet
6.24.1 Crystal oscillator
6.24.2 PLLs
6.23 Reset
6.24 Clocking and power control
Reset is accomplished by an active low signal on the RESET_N input pin. A reset pulse
with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to
guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the
oscillator to start up and stabilize after V
with a minimum duration of 10 clock pulses will also be applied if the watchdog timer
generates an internal device reset.
Clocking in the LPC3180 is designed to be versatile, so that system and peripheral
requirements may be met, while allowing optimization of power consumption. Clocks to
most functions may be turned off if not needed, some peripherals do this automatically.
The LPC3180 includes three operational modes that give control over processing speed
and power consumption. In addition, clock rates to different functional blocks may be
controlled by changing clock sources, reconfiguring PLL values, or altering clock divider
configurations. This allows a trade-off of power versus processing speed based on
application requirements.
The main oscillator is the basis for the clocks most chip functions use by default.
Optionally, many functions can be clocked instead by the output of a PLL (with a fixed
397x rate multiplication) which runs from the RTC oscillator. In this mode, the main
oscillator may be turned off unless the USB interface is enabled. If a SYSCLK frequency
other than 13 MHz is required in the application, or if the USB block is not used, the main
oscillator may be used with a frequency of between 1 MHz and 20 MHz.
The LPC3180 includes three PLLs: one allows boosting the RTC frequency to
13.008896 MHz for use as the primary system clock; one provides the 48 MHz clock
required by the USB block; and one provides the basis for the CPU clock, the AHB bus
clock, and the main peripheral clock.
The first PLL multiplies the 32768 Hz RTC clock by 397 to obtain a 13.008896 MHz clock.
The 397x PLL is designed for low power operation and low jitter. This PLL requires an
external RC loop filter for proper operation.
The other two PLLs accept an input clock from either the main oscillator or the output of
the 397x PLL. The input frequency is multiplied up to a higher frequency, then divided
down to provide the output clock.
The PLL input may initially be divided down by a pre-divider value ‘N’, which may have the
values 1, 2, 3, or 4. This pre-divider can allow a greater number of possibilities for the
output frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the pre-divider
output by a value ‘M’, in the range of 1 through 256. The resulting frequency must be in
the range of 156 MHz to 320 MHz. The multiplier works by dividing the output of a Current
Controlled Oscillator (CCO) by the value of M, then using a phase detector to compare the
divided CCO output to the pre-divider output. The error value is used to adjust the CCO
frequency.
Rev. 02 — 15 February 2007
16/32-bit ARM microcontroller with external memory interface
DD
reaches operational voltage. An internal reset
LPC3180
© NXP B.V. 2007. All rights reserved.
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