P87C552 NXP Semiconductors, P87C552 Datasheet - Page 48

• Manufacturer Part Number: P87C552
• Description: The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in anadvanced CMOS process and is a derivative of the 80C51microcontroller family
• Manufacturer: NXP Semiconductors

Philips Semiconductors
I
An I
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the
SIO1 hardware cannot resolve this type of problem. When this
occurs, the problem must be resolved by the device that is pulling
the SCL bus line LOW.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see Figure
45). The SIO1 hardware transmits additional clock pulses when the
STA flag is set, but no START condition can be generated because
the SDA line is pulled LOW while the I
The SIO1 hardware attempts to generate a START condition after
every two additional clock pulses on the SCL line. When the SDA
line is eventually released, a normal START condition is transmitted,
state 08H is entered, and the serial transfer continues.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO1
2003 Apr 01
2
C B
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I
capture/compare, high I/O, low voltage (2.7 V to 5.5 V), low power
2
C bus hang-up occurs if SDA or SCL is pulled LOW by an
US
O
BSTRUCTED BY A
08H
S
STA FLAG
SDA LINE
SCL LINE
SLA
L
OW
L
W
EVEL ON
Figure 43. Simultaneous Repeated START Conditions from 2 Masters
18H
2
A
C bus is considered free.
SCL
TIME OUT
OR
Figure 44. Forced Access to a Busy I
SDA
DATA
2
C, PWM,
OTHER MASTER SENDS REPEATED
START CONDITION EARLIER
28H
A
48
S
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems.
B
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
The SIO1 hardware only reacts to a bus error when it is involved in
a serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO1 immediately switches to the not
addressed slave mode, releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 10.
US
E
START CONDITION
BOTH MASTERS CONTINUE
WITH SLA TRANSMISSION
RROR
2
C Bus
SU00975
SU00976
P87C552
Product data