P89LPC9381 NXP Semiconductors, P89LPC9381 Datasheet - Page 19

• Manufacturer Part Number: P89LPC9381
• Description: The P89LPC9381 is a single-chip microcontroller, available in low-cost packages, basedon a high performance processor architecture that executes instructions in two to fourclocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

Philips Semiconductors
P89LPC9381_1
Product data sheet
7.10 Memory organization
7.7 CCLK wake-up delay
7.8 CCLK modification: DIVM register
7.9 Low power select
The P89LPC9381 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 to 100 s. If the clock source is either the internal RC oscillator, watchdog oscillator, or
external clock, the delay is 224 OSCCLK cycles plus 60 s to 100 s.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC9381 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.
This bit can then be set in software if CCLK is running at 8 MHz or slower.
The various P89LPC9381 memory spaces are as follows:
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DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
IDATA
Indirect Data. 256 B of internal data memory space (00H:FFH) accessed via indirect
addressing using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area. This area includes the DATA area and the 128 B immediately
above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
Rev. 01 — 8 September 2006
8-bit microcontroller with 10-bit ADC
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
P89LPC9381
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