XA-H4 NXP Semiconductors, XA-H4 Datasheet - Page 26

• Manufacturer Part Number: XA-H4
• Description: The powerful 16-bit XA CPU core and rich feature set make the XA-H3 and XA-H4 devices ideal for high-performance real-time applications such as industrial control and networking
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 7. USART0 Interrupts (Interrupt structure is the same, except for bit locations, for all 4 USARTs)
EXCEPTION/TRAPS PRECEDENCE
1999 Sep 24
Rx Character Available
SDLC EOF
(XA-H4 Only)
CRC/Framing Error
Rx Overrun
Parity Error
Tx Buffer Empty
Break/Abort
Tx Underrun/EOM
CTS
SYNC/HUNT
(XA-H4 Only)
DCD
Zero Count
Reset (h/w, watchdog, s/w)
Break Point
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
Single-chip 16-bit microcontroller
Potential
Interrupt
USART0
Description
WR1[2]
802[2]
See WR1[1]
Break/
Abort IE
WR15[7]
81E[7]
Tx Underrun/EOM IE
WR15[6]
81E[6]
CTS IE
WR15[5]
81E[5]
SYNC/
HUNT IE
WR15[4]
81E[4]
DCD IE
WR15[3]
81E[3]
Zero Count IE
WR15[1]
81E[1]
Individual Enable Bit
MMR Hex Offset
–
–
–
–
RR0[0]
820[0]
RR1[7]
822[7]
RR1[6]
822[6]
RR1[5]
822[5]
RR1[4]
822[4]
RR0[2]
820[2]
RR0[7]
820[7]
RR0[6]
820[6]
RR0[5]
820[5]
RR0[4]
822[4]
RR0[3]
820[3]
RR0[1]
820[1]
MMR Hex Offset
Source Bit
Vector Address
000C–000F
0008–000B
0000–0003
0004–0007
0010–0013
0014–0017
0040–007F
26
WR1[4:3]
802[4:3]
Tx Interrupt Enable
WR1[1]
802[1]
Master External/Status
Interrupt Enable
WR1[0]
802[0]
Group Enable Bit(S)
MMR Hex Offset
Even Channel Rx IP
RR3[5]
826[5]
Even Channel Tx IP
RR3[4]
826[4]
Even Channel
External/Status IP
RR3[3]
826[3]
MMR Hex Offset
Group Flag Bit
Arbitration Ranking
0 (High)
1
1
1
1
1
1
Preliminary specification
USART0/1 Master
Interrupt Enable
WR9[3]
812[3]
Master Enable Bit
MMR Hex Offset
XA-H4