MPT612 NXP Semiconductors, MPT612 Datasheet - Page 11

• Manufacturer Part Number: MPT612
• Description: The MPT612, the first dedicated IC for performing the Maximum Power Point Tracking (MPPT) function, is designed for use in applications that use solar photovoltaic (PV) cells or in fuel cells
• Manufacturer: NXP Semiconductors

NXP Semiconductors
MPT612
Product data sheet
7.5.1 Interrupt sources
7.6 Pin connect block
7.7 Fast general purpose parallel I/O
from the interrupt vector location. If more than one request is assigned to the FIQ class,
the FIQ service routine reads a word from the VIC that identifies which FIQ sources are
requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots. Slot 0 has the highest priority and slot 15 has the lowest priority.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to generate
the IRQ signal for the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping to it. If any vectored IRQs are pending, the VIC
provides the address of the highest priority requesting IRQs service routine, otherwise it
provides the address of a default routine which is shared by all the non-vectored IRQs.
The default routine can read another VIC register to see which IRQs are active.
Each peripheral device has one interrupt line connected to the VIC which can contain
several internal interrupt flags. Each individual interrupt flag can represent more than one
interrupt source.
The pin connect block enables selected device pins to have more than one function.
Configuration registers control the multiplexers to allow connection between the pin and
the on chip peripherals. Peripherals should be connected to the appropriate pins before
being activated and any related interrupt(s) are enabled. Activity of any enabled
peripheral function that is not mapped to a related pin should be considered undefined.
The pin control module with its pin select registers defines the functionality of the
processor core in a given hardware environment.
After reset, all pins of PIO are configured as inputs with the following exception:
Pins that are not connected to a specific peripheral function are controlled by the GPIO
registers. Pins can be dynamically configured as inputs or outputs. Separate registers
allow simultaneous setting or clearing any number of outputs. The value of the output
register and the state of the port pins can be read back. The GPIO provides the following
features:
• If the JTAGSEL pin is HIGH (Debug mode enabled), the JTAG pins will assume their
• GPIO registers are relocated for the fastest possible I/O timing
• Mask registers allow sets of port bits to be treated as a group, leaving other bits
• All GPIO registers are byte addressable
• Entire port value can be written in one instruction
• Bit level set and clear registers allow a single instruction setting or clearing of any
• Direction control of individual bits
JTAG functionality for use with EmbeddedICE and cannot be configured via the pin
connect block.
unchanged
number of bits on one port
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 September 2010
Maximum power point tracking IC
© NXP B.V. 2010. All rights reserved.
MPT612
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