EP4SE820H40C4N Altera Corporation, EP4SE820H40C4N Datasheet - Page 55

• Manufacturer Part Number: EP4SE820H40C4N
• Description: IC STRATIX IV FPGA 820K 1517HBGA
• Manufacturer: Altera Corporation
• Series: STRATIX® IV Er

Specifications of EP4SE820H40C4N

• Number Of Logic Elements/cells: 813050
• Number Of Labs/clbs: 32522
• Total Ram Bits: 34093056
• Number Of I /o: 976
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-BBGA Exposed Pad
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–34. PLL Specifications for Stratix IV Devices (Part 1 of 2)—Preliminary
December 2011 Altera Corporation
f
f
f
t
f
f
t
t
t
t
f
t
t
f
t
t
t
t
IN
INPFD
VCO
EINDUTY
OUT
OUT_EXT
OUTDUTY
FCOMP
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
CLBW
PLL_PSERR
ARESET
INCCJ
OUTPJ_DC
Symbol
(2)
(4),
(6)
(5)
Input clock frequency (–2/–2x speed grade)
Input clock frequency (–3 speed grade)
Input clock frequency (–4 speed grade)
Input frequency to the PFD
PLL VCO operating range (–2 speed grade)
PLL VCO operating range (–3 speed grade)
PLL VCO operating range (–4 speed grade)
Input clock or external feedback clock input duty cycle
Output frequency for internal global or regional clock
(–2/–2x speed grade)
Output frequency for internal global or regional clock
(–3 speed grade)
Output frequency for internal global or regional clock
(–4 speed grade)
Output frequency for external clock output (–2 speed grade)
Output frequency for external clock output (–3 speed grade)
Output frequency for external clock output (–4 speed grade)
Duty cycle for external clock output (when set to 50%)
External feedback clock compensation time
Time required to reconfigure scan chain
Time required to reconfigure phase shift
scanclk frequency
Time required to lock from end-of-device configuration or
de-assertion of areset
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on the areset signal
Input clock cycle to cycle jitter (F
Input clock cycle to cycle jitter (F
Period Jitter for dedicated clock output (F
Period Jitter for dedicated clock output (F
PLL Specifications
Table 1–34
(0° to 85°C), industrial (–40° to 100°C), and military (–55°C to 125°C) junction
temperature ranges.
lists the Stratix IV PLL specifications when operating in the commercial
Parameter
REF
REF
(8)
< 100 MHz)
≥ 100 MHz)
OUT
OUT
≥ 100 MHz)
< 100 MHz)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Min
600
600
600
40
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
5
5
5
5
Typ
3.5
0.3
1.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
1
4
800
717
717
800
717
717
800
717
717
1600
1300
1300
±750
Max
0.15
17.5
325
100
±50
175
60
55
10
—
—
—
—
—
—
1
1
(1)
(1)
(1)
(3)
(3)
(3)
(3)
(3)
(3)
mUI (p-p)
UI (p-p)
ps (p-p)
ps (p-p)
scanclk
scanclk
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ns
ps
ns
%
%
1–47