EP4SE820H40C4N Altera Corporation, EP4SE820H40C4N Datasheet - Page 69

• Manufacturer Part Number: EP4SE820H40C4N
• Description: IC STRATIX IV FPGA 820K 1517HBGA
• Manufacturer: Altera Corporation
• Series: STRATIX® IV Er

Specifications of EP4SE820H40C4N

• Number Of Logic Elements/cells: 813050
• Number Of Labs/clbs: 32522
• Total Ram Bits: 34093056
• Number Of I /o: 976
• Number Of Gates: -
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-BBGA Exposed Pad
• Lead Free Status: Lead free
• Rohs Status: RoHS Compliant

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
I/O Timing
I/O Timing
December 2011 Altera Corporation
f
Figure 1–7
Figure 1–7. Timing Diagram for the oe and dyn_term_ctrl Signals
Duty Cycle Distortion (DCD) Specifications
Table 1–50
Table 1–50. Worst-Case DCD on Stratix IV I/O Pins
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O Timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
The Excel-based I/O Timing spreadsheet is downloadable from the
Stratix IV Devices
Output Duty Cycle
dyn_term_ctrl
Symbol
shows the timing diagram for the oe and dyn_term_ctrl signals.
lists the worst-case DCD for Stratix IV devices.
R
oe
X
webpage.
T
Tristate
RS_RT
Min
45
Speed Grade
–2/–2×
Max
55
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Min
Speed Grade
45
T
–3
X
Max
55
Min
Speed Grade
45
–4
Max
55
Literature:
T
Tristate
RS_RT
Unit
%
R
X
1–61