STM32F415ZG STMicroelectronics, STM32F415ZG Datasheet - Page 113
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STM32F415ZG
Manufacturer Part Number
STM32F415ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator, HW crypto
Manufacturer
STMicroelectronics
Datasheet
1.STM32F415ZG.pdf
(168 pages)
Specifications of STM32F415ZG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Cryptographic Acceleration
hardware acceleration for AES 128, 192, 256, Triple DES, HASH (MD5, SHA-1), and HMAC
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F415ZGT6
Manufacturer:
VISHAY
Quantity:
5 000
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STM32F415xx, STM32F417xx
Figure 40. I
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
Figure 41. I
1. Based on characterization, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
SD transmit
SD receive
byte.
byte.
WS output
SD transmit
SD receive
CPOL = 0
CPOL = 1
WS input
CPOL = 0
CPOL = 1
2
2
S slave timing diagram (Philips protocol)
S master timing diagram (Philips protocol)
t v(WS)
t su(WS)
t w(CKH)
t w(CKH)
LSB receive
Doc ID 022063 Rev 2
LSB transmit
LSB transmit
t su(SD_MR)
LSB receive
t su(SD_SR)
t c(CK)
(2)
t c(CK)
(2)
(2)
(2)
MSB receive
MSB transmit
MSB receive
DD
MSB transmit
t w(CKL)
and 0.7 × V
t w(CKL)
t f(CK)
(1)
t h(SD_MR)
DD
(1)
t v(SD_MT)
.
Bitn receive
t v(SD_ST)
t h(SD_SR)
Bitn transmit
Bitn transmit
Bitn receive
Electrical characteristics
t r(CK)
LSB receive
t h(WS)
t h(SD_MT)
LSB transmit
t h(WS)
t h(SD_ST)
LSB transmit
LSB receive
ai14884b
ai14881b
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