STM32F405ZG STMicroelectronics, STM32F405ZG Datasheet - Page 54
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STM32F405ZG
Manufacturer Part Number
STM32F405ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator
Manufacturer
STMicroelectronics
Datasheet
1.STM32F405VG.pdf
(167 pages)
Specifications of STM32F405ZG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F405ZGT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F405ZGT6
Manufacturer:
ST
Quantity:
20 000
Pinouts and pin description
Table 6.
1. Function availability depends on the chosen device.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
54/167
59 93 137 B5 165
60 94 138 D6 166
61 95 139 A5 167
62 96 140 B4 168
63 99
64
-
-
-
-
-
-
-
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website:
www.st.com.
97 141 A4 169
98 142 A3 170
10
Pin number
0
- 143 C6 171
-
-
-
-
144 C5 172
-
-
-
-
-
STM32F40x pin and ball definitions (continued)
D5
D4 173
C4 174
C3 175
C2 176
-
(function after
Pin name
PDR_ON
reset)
BOOT0
PB7
PB8
PB9
PE0
PE1
V
V
PI4
PI5
PI6
PI7
SS
DD
(1)
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
S
S
I
I
Doc ID 022152 Rev 2
FT
B
TIM4_ETR / FSMC_NBL0 /
USART1_RX/ TIM4_CH2/
FSMC_NBL1 / DCMI_D3/
TIM10_CH1 / DCMI_D6 /
TIM4_CH4/ TIM11_CH1/
I2C1_SDA / FSMC_NL /
TIM8_BKIN / DCMI_D5/
I2C1_SDA / CAN1_TX/
DCMI_D2/ EVENTOUT
TIM8_CH2 / DCMI_D6/
TIM8_CH3 / DCMI_D7/
I2C1_SCL/ CAN1_RX/
SPI2_NSS/ I2S2_WS /
SDIO_D5 / DCMI_D7 /
TIM4_CH3/SDIO_D4/
Alternate functions
ETH_MII_TXD3 /
DCMI_VSYNC /
DCMI_VSYNC/
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
EVENTOUT
TIM8_CH1 /
EVENTOUT
EVENTOUT
EVENTOUT
STM32F405xx, STM32F407xx
Additional functions
V
PP