STM32F405ZG STMicroelectronics, STM32F405ZG Datasheet - Page 90
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STM32F405ZG
Manufacturer Part Number
STM32F405ZG
Description
High-performance and DSP with FPU, ARM Cortex-M4 MCU with 1 Mbyte Flash, 168 MHz CPU, Art Accelerator
Manufacturer
STMicroelectronics
Datasheet
1.STM32F405VG.pdf
(167 pages)
Specifications of STM32F405ZG
Core
ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
3×12-bit, 2.4 Msps A/d Converters
up to 24 channels and 7.2 MSPS in triple interleaved mode
General-purpose Dma
16-stream DMA controller with FIFOs and burst support
Up To 17 Timers
up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
10/100 Ethernet Mac With Dedicated Dma
supports IEEE 1588v2 hardware, MII/RMII
Rtc
subsecond accuracy, hardware calendar
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F405ZGT6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
STM32F405ZGT6
Manufacturer:
ST
Quantity:
20 000
Electrical characteristics
Table 32.
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Based on characterization, not tested in production.
Table 33.
90/167
Jitter
I
I
f
f
f
t
Jitter
DD(PLL)
DDA(PLL)
PLLI2S_IN
PLLI2S_OUT
VCO_OUT
LOCK
between PLL and PLLI2S.
Symbol
Symbol
(3)
(4)
(4)
(4)
Main PLL characteristics (continued)
PLLI2S (audio PLL) characteristics
Cycle-to-cycle jitter
Period Jitter
Main clock output (MCO) for
RMII Ethernet
Main clock output (MCO) for MII
Ethernet
Bit Time CAN jitter
PLL power consumption on VDD
PLL power consumption on
VDDA
PLLI2S input clock
PLLI2S multiplier output clock
PLLI2S VCO output
PLLI2S lock time
Master I2S clock jitter
WS I2S clock jitter
Parameter
Parameter
(2)
Doc ID 022152 Rev 2
VCO freq = 192 MHz
VCO freq = 432 MHz
Cycle to cycle at
12,343 MHz on
48KHz period,
N=432, P=4, R=5
Average frequency of
12,343 MHz
N = 432, P = 4, R = 5
on 256 samples
Cycle to cycle at 48 KHz
on 1000 samples
System clock
120 MHz
Cycle to cycle at 50 MHz
on 1000 samples
Cycle to cycle at 25 MHz
on 1000 samples
Cycle to cycle at 1 MHz
on 1000 samples
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
(1)
Conditions
Conditions
peak
to
peak
peak
to
peak
RMS
RMS
RMS
peak
peak
to
0.15
0.45
0.30
0.55
Min
0.95
STM32F405xx, STM32F407xx
-
-
-
-
-
-
-
TBD
Min
192
100
75
-
-
-
-
(3)
±150
±200
Typ
330
25
15
32
40
-
-
±280
Typ
400
90
1
-
-
-
-
-
Max
0.40
0.75
0.40
0.85
TBD
Max
2.10
216
432
200
300
-
-
-
-
-
-
-
-
-
-
Unit
mA
mA
MHz
MHz
MHz
Unit
ps
µs
ps
ps
ps