ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 70

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

On-chip peripherals
Caution:
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A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced
watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the
WDGRF bit has to be set.
The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the
reset. It is automatically cleared after it has been read.
When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is
enabled (by hardware or software), the microcontroller will be immediately reset.
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGE bit in the LTCSR is not used.
Refer to the option byte description in the "device configuration and ordering information"
section.
Using Halt mode with the watchdog (option)
If the Watchdog reset on Halt option is not selected by option byte, the Halt mode can be
used when the watchdog is enabled.
In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite
Timer stops counting and is no longer able to generate a Watchdog reset until the
microcontroller receives an external interrupt or a reset.
If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset state).
If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
Figure 35. Watchdog timing diagram
Input capture
The 8-bit input capture register is used to latch the free-running upcounter after a rising or
falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and
the LTICR register contains the MSB of the free-running upcounter. An interrupt is
generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always contains the data from the last input capture.
Input capture is inhibited if the ICF bit is set.
WDGD BIT
INTERNAL
WATCHDOG
RESET
f
WDG
(2ms @ 8 MHz f
t
WDG
SOFTWARE SETS
OSC
WDGD BIT
)
HARDWARE CLEARS
WDGD BIT
ST7LITEU05 ST7LITEU09
WATCHDOG RESET