ST7LITEU09 STMicroelectronics, ST7LITEU09 Datasheet - Page 74

• Manufacturer Part Number: ST7LITEU09
• Description: ST7ULTRALITE - 8-BIT MCU WITH 2K SINGLE VOLTAGE FLASH MEMORY, ADC, TIMERS
• Manufacturer: STMicroelectronics

Specifications of ST7LITEU09

• 2k Bytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• 128 Bytes Data Eeprom. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C
• Clock Sources: internal trimmable 8MHz RC oscillator, internal low power, low frequency RC oscillator or external clock
• Five Power Saving Modes: Halt, Auto Wake Up from Halt, Active-Halt, Wait and Slow
• One 8-bit Lite Timer (lt) With Prescaler Including: watchdog, 1 realtime base and 1 input capture

On-chip peripherals
11.2
11.2.1
11.2.2
11.2.3
Note:
74/139
12-bit autoreload timer (AT)
Introduction
The 12-bit Autoreload Timer can be used for general-purpose timing functions. It is based
on a free-running 12-bit upcounter with a PWM output channel.
Main features
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●
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Figure 37. Block diagram
Functional description
PWM mode
This mode allows a pulse width modulated signals to be generated on the PWM0 output pin
with minimum core processing overhead. The PWM0 output signal can be enabled or
disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is
configured as output push-pull alternate function.
CMPF0 is available in PWM mode (see PWM0CSR description
12-BIT DUTY CYCLE VALUE (shadow)
12-bit upcounter with 12-bit autoreload register (ATR)
Maskable overflow interrupt
PWM signal generator
Frequency range 2 kHz - 4 MHz (@ 8 MHz f
–
–
–
Output compare function
Preload
DCR0H
f
(1 ms timebase
@ 8 MHz)
LTIMER
f
CPU
Programmable duty-cycle
Polarity control
Maskable compare interrupt
Preload
DCR0L
on OVF Event
IF OE0=1
0
7
ATCSR
0
0
f
COUNTER
CK1
OE0 bit
1
0
CNTR
ATR
CK0
CMPF0 bit
COMP-
PARE
12-BIT AUTORELOAD VALUE
OVF
12-BIT UPCOUNTER
CPU
OVFIE
)
CMPIE
CMPF0
0
Update on OVF Event
OVF INTERRUPT
REQUEST
f
PWM
on page
ST7LITEU05 ST7LITEU09
OP0 bit
POL-
ARITY
OE0 bit
80).
CMP INTERRUPT
REQUEST
PWM0