ST72325S4 STMicroelectronics, ST72325S4 Datasheet - Page 181

• Manufacturer Part Number: ST72325S4
• Description: 8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72325S4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72325 devices are ROM versions. ST72P325
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-pro-
grammed HDFlash devices. FLASH devices are
14.1 FLASH OPTION BYTES
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC
clock source enabled. In masked ROM devices,
the option bytes are fixed in hardware by the ROM
code (see option list).
OPTION BYTE 0
OPT7= WDG HALT Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which includes the
clock filter and the backup safe oscillator.
0: CSS enabled
Default
7
1
WDG
1
STATIC OPTION BYTE 0
1
1
0
VD
0
0
1
1
1
0
shipped to customers with a default content, while
ROM/FASTROM factory coded parts contain the
code supplied by the customer. This implies that
FLASH devices have to be configured by the cus-
tomer using the Option Bytes while the ROM/FAS-
TROM devices are factory-configured.
1: CSS disabled
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to
12.3.2 on page 145
OPT2 = Reserved, must be kept at default value.
OPT1= PKG0 Package selection bit 0
This option bit is not used.
Lowest Threshold: (V
Med. Threshold (V
Highest Threshold (V
1
17
Selected Low Voltage Detector
1
LVD and AVD Off
OSCTYPE
STATIC OPTION BYTE
1
1
DD
~3.5V)
DD
DD
0
0
~3V)
~4V)
2
1
OSCRANGE
1
1
ST72325xx
VD1
1
1
0
0
0
1
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VD0
1
0
1
0
0
1