ST72325S4 STMicroelectronics, ST72325S4 Datasheet - Page 7

• Manufacturer Part Number: ST72325S4
• Description: 8-BIT MCU WITH 16 TO 60K FLASH/ROM, ADC, CSS, FIVE TIMERS, SPI, SCI, I2C INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72325S4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt,Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

1 DESCRIPTION
The ST72F325 Flash and ST72325 ROM devices
are members of the ST7 microcontroller family de-
signed for mid-range applications.
They are derivatives of the ST72321 and ST72324
devices, with enhanced characteristics and robust
Clock Security System.
All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set and are available with Flash or ROM pro-
gram memory. The ST7 family architecture offers
both power and flexibility to software developers,
enabling the design of highly efficient and compact
application code.
The on-chip peripherals include an A/D converter,
a PWM Autoreload timer, 2 general purpose tim-
ers, I
For power economy, microcontroller can switch
dynamically into WAIT, SLOW, ACTIVE-HALT or
Figure 1. Device Block Diagram
(8 bits on AR devices)
(2 bits on C/J/K devices)
1)
(8 bits on AR devices)
(6 bits on C/J devices)
(5 bits on K devices)
(8 bits on AR devices)
(6 bits on C/J devices)
(2 bits on K devices)
ROM devices have up to 32 Kbytes of program memory and up to 1 Kbyte of RAM.
2
C bus, SPI interface and an SCI interface.
RESET
PF7:0
OSC1
OSC2
V
PD7:0
V
EVD
AREF
PE7:0
V
V
V
TLI
SSA
DD
SS
PP
MCC/RTC/BEEP
8-BIT CORE
10-BIT ADC
CONTROL
TIMER A
PORT D
PORT F
PORT E
BEEP
AVD
OSC
ALU
LVD
SCI
HALT mode when the application is in idle or
stand-by state.
Typical applications are consumer, home, office
and industrial products.
(DM) to support in-circuit debugging (ICD). For a
description of the DM registers, refer to the ST7
ICC Protocol Reference Manual.
Main Differences with ST72321:
– LQFP48 and LQFP32 packages
– Clock Security System
– Internal RC, Readout protection, LVD and PLL
– Negative current injection not allowed on I/O port
– External interrupts have Exit from Active Halt
The devices feature an on-chip Debug Module
without limitations
PB0 (instead of PC6).
mode capability.
(512 - 2048 Bytes
(16K - 60K Bytes
DEBUG MODULE
WATCHDOG
PROGRAM
PWM ART
MEMORY
TIMER B
PORT C
PORT A
PORT B
RAM
I2C
SPI
1)
1)
)
)
(8 bits)
PC7:0
PA7:0
(8 bits on AR devices)
(5 bits on C/J devices)
(4 bits on K devices)
PB7:0
(8 bits on AR devices)
(5 bits on C/J devices)
(3 bits on K devices)
ST72325xx
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