ST7LITE25F2 STMicroelectronics, ST7LITE25F2 Datasheet - Page 94

• Manufacturer Part Number: ST7LITE25F2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LITE25F2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7LITE2
13.3.2 Operating conditions with Low Voltage Detector (LVD)
T
Notes:
1. Not tested in production.
2. Not tested in production. The V
When the V
3. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
recommended to pull V
page 112
13.3.3 Auxiliary Voltage Detector (AVD) Thresholds
T
Note:
1. Not tested in production.
13.3.4 Internal RC Oscillator and PLL
The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).
94/133
1
V
V
V
Vt
t
I
V
V
V
∆V
V
V
V
t
A
A
g(VDD)
DD(LVD
STARTUP
Symbol
Symbol
Symbol
IT+
IT-
hys
IT+
IT-
hys
DD(RC)
DD(x4PLL)
DD(x8PLL)
POR
= -40 to 85°C, unless otherwise specified
= -40 to 85°C, unless otherwise specified
IT-
(LVD)
(AVD)
(LVD)
(AVD)
)
and note 4.
DD
Reset release threshold
(V
Reset generation threshold
(V
LVD voltage threshold hysteresis
V
Filtered glitch delay on V
LVD/AVD current consumption
1=>0 AVDF flag toggle threshold
(V
0=>1 AVDF flag toggle threshold
(V
AVD voltage threshold hysteresis
Voltage drop between AVD flag set
and LVD reset activation
Internal RC Oscillator operating voltage
x4 PLL operating voltage
x8 PLL operating voltage
PLL Startup time
DD
slope is outside these values, the LVD may not ensure a proper reset of the MCU.
DD
DD
DD
DD
rise time rate
rise)
fall)
rise)
fall)
DD
Parameter
Parameter
down to 0V to ensure optimum restart conditions. Refer to circuit example in
Parameter
2)3)
DD
rise time rate condition is needed to insure a correct device power-on and LVD reset.
DD
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
Not detected by the LVD
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
V
V
IT+
IT+
DD
(LVD)
(AVD)
fall
Conditions
Conditions
-V
-V
IT-
IT-
Conditions
(LVD)
(AVD)
3.40
2.65
4.00
4.40
3.90
3.20
3.80
3.20
2.40
4.30
3.70
2.90
Min
Min
20
Min
2.4
2.4
3.3
1)
1)
1)
1)
1)
1)
Typ
Typ
4.25
3.60
2.90
4.05
3.40
2.70
4.70
4.10
3.40
4.60
3.90
3.20
0.45
200
220
150
Typ
60
4.30
3.65
20000
2.90
4.90
4.10
3.40
Max
Max
4.50
3.80
3.15
5.00
4.30
3.60
150
Max
5.5
3.3
5.5
Figure 84 on
1)
1)
1)
1)
1)
1)
cycles
µs/V
Unit
Unit
(f
clock
input
mV
mV
Unit
PLL
µA
ns
V
V
V
PLL
V
)