ST92150CV1Q-Auto STMicroelectronics, ST92150CV1Q-Auto Datasheet - Page 167

• Manufacturer Part Number: ST92150CV1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92150CV1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

10.3 EXTENDED FUNCTION TIMER (EFT)
10.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the
prescaler.
10.3.2 Main Features
■
■
■
■
■
■
■
■
■
The Block Diagram is shown in
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– Maskable interrupt generation
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– Maskable interrupt generation
Programmable prescaler: INTCLK divided by 2,
4 or 8.
Overflow status flag and maskable interrupts
External clock input (must be at least 4 times
slower than the INTCLK clock speed) with the
choice of active edge
Output compare functions with
Input capture functions with
Pulse width modulation mode (PWM)
One pulse mode
5 alternate functions on I/O ports
Global Timer interrupt (EFTI).
Figure
91.
INTCLK
ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
Table 35. EFT Pin Naming conventions
10.3.3 Functional Description
10.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
Counter Registers
Alternate Counter Registers
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
value in the counter register repeats every
131.072, 262.144 or 524.288 INTCLK cycles de-
pending on the CC[1:0] bits.
Function
Input Capture 1 - ICAP1
Input Capture 2 - ICAP2
Output Compare 1 - OCMP1 OCMPA0
Output Compare 2 - OCMP2 OCMPB0
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MSB).
nificant byte (LSB).
m ost significant byte (MSB).
least significant byte (LSB).
page
169).
EFT0
ICAPA0
ICAPB0
Table
EFT1
OCMPA1
OCMPB1
ICAPA1
ICAPB1
36. The
167/430
9