ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet
ST72321AR9-Auto
Specifications of ST72321AR9-Auto
Related parts for ST72321AR9-Auto
ST72321AR9-Auto Summary of contents
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... Development tools ■ Full hardware/software development package, ICT capability Table 1. Device summary Reference ST72321AR6-Auto, ST72321R6-Auto, ST72321AR7-Auto, ST72321xx-Auto ST72321J7-Auto, ST72321R7-Auto ST72321AR9-Auto, ST72321J9-Auto, ST72321R9-Auto Doc ID 13829 Rev 1 LQFP64 LQFP44 Part number 1/243 www.st.com 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72321xx-Auto 6.4 Multi-oscillator (MO ...
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Contents 9.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72321xx-Auto 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.2.8 12.2.9 12.3 ART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 13.7.4 13.7.5 13.7.6 13.7.7 13.7.8 13.7.9 13.7.10 Counter high register (CHR ...
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ST72321xx-Auto 15 Serial communications interface (SCI 135 15.1 Introduction . . . . . . . ...
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Contents 16.7.2 16.7.3 16.7.4 16.7.5 16.7.6 16.7.7 17 10-bit A/D converter (ADC ...
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ST72321xx-Auto 19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 19.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 19.9.2 19.10 Timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 19.11 Communication ...
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ST72321xx-Auto 22.1.7 22.1.8 22.1.9 22.1.10 I 22.1.11 Readout protection with LVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72321xx-Auto Table 49. PWM frequency versus resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 140. Flash option bytes 223 Table 141. Option byte 0 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Table 142. Option byte 1 bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 143. Package selection (OPT7 225 Table 144. STMicroelectronics development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 145. Suggested list of socket types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 146. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 14/243 ...
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ST72321xx-Auto List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 49. Output compare timing diagram, fTIMER = fCPU ...
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ST72321xx-Auto Figure 101. ADC error classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... I For power economy, the microcontroller can switch dynamically into Wait, Slow, Active Halt or Halt mode when the application is in idle or standby state. Table 2. Product overview Reference Program memory ST72321R9-Auto 60 Kbytes ST72321AR9-Auto Flash/ROM ST72321J9-Auto ST72321R7-Auto 48 Kbytes ST72321AR7-Auto Flash/ROM ST72321J7-Auto ST72321R6-Auto ...
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ST72321xx-Auto Figure 1. Device block diagram RESET V PP TLI EVD OSC1 OSC2 PF7:0 (8-bits) PE7:0 (8-bits) PD7:0 (8-bits) V AREF V SSA 8-bit CORE ALU CONTROL (1024 or 2048 bytes) LVD AVD OSC MCC/RTC/BEEP PORT ...
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Package pinout and pin description 2 Package pinout and pin description 2.1 Package pinout Figure 2. 64-pin LQFP 14x14 and 10x10 package pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 PWM3 / PB0 5 PWM2 ...
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ST72321xx-Auto Figure 3. 44-pin LQFP package pinout RDI / PE1 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 / PB3 ARTCLK / (HS) PB4 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / ...
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Package pinout and pin description 2.2 Pin description In the device pin description table, the RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Refer to Section ...
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ST72321xx-Auto Table 3. Device pin description (continued) Pin No. Pin name 25 15 PF0/MCO/AIN8 26 16 PF1 (HS)/BEEP 27 17 PF2 (HS) PF3/OCMP2_A AIN9 PF4/OCMP1_A AIN10 PF5/ICAP2_A AIN11 31 19 PF6(HS)/ICAP1_A I/O C PF7(HS)/ ...
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Package pinout and pin description Table 3. Device pin description (continued) Pin No. Pin name 41 29 PC6/SCK/ICCCLK I PC7/SS/AIN15 43 PA0 - 44 PA1 - 45 - PA2 46 31 PA3(HS) ( DD_1 ...
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ST72321xx-Auto Table 3. Device pin description (continued) Pin No. Pin name PE2 (Flash device PE2 (ROM device) 64 PE3 - mandatory to connect all available V 2. OSC1 and OSC2 pins connect a crystal/ceramic resonator ...
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Register and memory map 3 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations Kbytes of RAM and Kbytes of user program memory. ...
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ST72321xx-Auto Table 4. Hardware register map (continued) Address Block Register label 000Ch PEDR 000Dh Port E PEDDR 000Eh PEOR 000Fh PFDR 0010h Port F PFDDR 0011h PFOR 0018h I2CCR 0019h I2CSR1 001Ah I2CSR2 2 001Bh I C I2CCCR 001Ch I2COAR1 ...
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Register and memory map Table 4. Hardware register map (continued) Address Block Register label 0040h 0041h TBCR2 0042h TBCR1 0043h TBCSR 0044h TBIC1HR 0045h TBIC1LR 0046h TBOC1HR 0047h TBOC1LR 0048h TIMER B TBCHR 0049h TBCLR 004Ah TBACHR 004Bh TBACLR 004Ch ...
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ST72321xx-Auto 4 Flash program memory 4.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a byte-by- byte basis using ...
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Flash program memory Figure 5. Memory map and sector address 4K 1000h 3FFFh 7FFFh 9FFFh BFFFh D7FFh DFFFh EFFFh FFFFh 4.3.1 Readout protection Readout protection, when selected, provides a protection against program memory content extraction and against write access to ...
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... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware interface on the application board (see to the device pinout description ...
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Flash program memory 4.6 IAP (in-application programming) This mode uses a BootLoader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a programming tool). This mode is fully controlled by user ...
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ST72321xx-Auto 5 Central processing unit (CPU) 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features ● Enable executing 63 basic instructions ● Fast 8-bit by 8-bit ...
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Central processing unit (CPU) 5.3.1 Accumulator (A) The accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. 5.3.2 Index registers (X and Y) These ...
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ST72321xx-Auto Arithmetic management bits Table 7. Bit Name Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero The result of the ...
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Central processing unit (CPU) The stack pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented after data has been pushed onto the stack and incremented before data is ...
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ST72321xx-Auto 6 Supply, reset and clock management 6.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An ...
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Supply, reset and clock management 6.3 Phase locked loop If the clock frequency input to the PLL is in the range MHz, the PLL can be used to multiply the frequency by two to obtain an f ...
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ST72321xx-Auto Crystal/ceramic oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of four oscillators with different frequency ranges has to be done by ...
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Supply, reset and clock management 6.5 Reset sequence manager (RSM) 6.5.1 Introduction The reset sequence manager includes three RESET sources as shown in ● External RESET source pulse ● Internal LVD RESET (low voltage detection) ● Internal WATCHDOG RESET These ...
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ST72321xx-Auto Figure 12. RESET sequence phases ACTIVE PHASE 6.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. This pull-up has no fixed value but varies in accordance with the ...
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Supply, reset and clock management 6.5.5 Internal watchdog RESET The RESET sequence generated by an internal Watchdog counter overflow is shown in Figure 13. Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is ...
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ST72321xx-Auto 6.6 System integrity management (SI) The System Integrity Management block contains the Low Voltage Detector (LVD) and Auxiliary Voltage Detector (AVD) functions managed by the SICSR register. 6.6.1 Low voltage detector (LVD) The low voltage detector function ...
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Supply, reset and clock management Figure 14. Low voltage detector versus reset IT+ V IT- RESET 6.6.2 Auxiliary voltage detector (AVD) The auxiliary voltage detector function (AVD) is based on an analog comparison between a V and ...
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ST72321xx-Auto Figure 15. Using the AVD to monitor IT+(AVD) V IT-(AVD) V IT+(LVD) V IT-(LVD) AVDF bit 0 AVD INTERRUPT REQUEST IF AVDIE bit = 1 LVD RESET Monitoring a voltage on the EVD pin This ...
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Supply, reset and clock management Figure 16. Using the voltage detector to monitor the EVD pin (AVDS bit = 1) V EVD V IT+(EVD) V IT-(EVD) AVDF 0 AVD INTERRUPT REQUEST IF AVDIE = 1 6.6.3 Low power modes Table ...
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ST72321xx-Auto 6.6.5 System Integrity (SI) Control/Status register (SICSR) SICSR 7 6 AVDS AVDIE RW RW SICSR description Table 13. Bit Name Voltage Detection selection 7 AVDS Voltage Detector interrupt enable 6 AVDIE Voltage Detector flag 5 AVDF LVD reset flag ...
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Supply, reset and clock management Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog); the LVDRF flag remains set to keep trace of the original failure. In this case, software can detect a ...
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ST72321xx-Auto 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...
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Interrupts Table 15. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 17. Interrupt processing flowchart RESET RESTORE PC FROM STACK Servicing pending interrupts As several ...
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ST72321xx-Auto When an interrupt request is not serviced immediately latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is ...
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Interrupts flag is set in the peripheral status registers and if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by ...
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ST72321xx-Auto Figure 20. Nested interrupt management IT1 IT2 RIM MAIN 7.5 Interrupt register description 7.5.1 CPU CC register interrupt bits CPU Table 16. CPU CC register interrupt bits description Bit Name 5 ...
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Interrupts Table 17. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable 1. TLI, TRAP and RESET events can interrupt a level 3 program. 7.5.2 Interrupt software priority registers (ISPRx) ...
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ST72321xx-Auto The TLI, RESET, and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Caution: If the I1_x and I0_x bits are modified while the interrupt x ...
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Interrupts Table 20. Interrupt mapping Source No. block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 MCC/RTC Main clock controller time base interrupt 2 ei0 External interrupt port A3..0 3 ei1 External interrupt port F2..0 4 ...
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ST72321xx-Auto 7.6 External interrupts 7.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the EICR register (Figure 21). This control allows to have up to four fully independent external interrupt ...
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Interrupts Figure 21. External interrupt control bits PORT A [3:0] INTERRUPTS PAOR.3 PADDR.3 PA3 IPA BIT PORT F [2:0] INTERRUPTS PFOR.2 PFDDR.2 PF2 PORT B [3:0] INTERRUPTS PBOR.3 PBDDR.3 PB3 IPB BIT PORT B [7:4] INTERRUPTS PBOR.7 PBDDR.7 PB7 58/243 ...
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ST72321xx-Auto 7.6.2 External interrupt control register (EICR) EICR 7 6 IS1[1:0] RW Table 21. EICR register description Bit Name ei2 and ei3 sensitivity 7:6 IS1[1:0] Interrupt polarity for port B 5 IPB ei0 and ei1 sensitivity 4:3 IS2[1:0] Interrupt polarity ...
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Interrupts Table 22. Interrupt sensitivity - ei2 (port B3..0) IS11 IS10 Table 23. Interrupt sensitivity - ei3 (port B7..4) IS11 IS10 Table 24. Interrupt ...
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ST72321xx-Auto Table 26. Nested interrupts register map and reset values Address (Hex.) Register label 0024h ISPR0 Reset value 0025h ISPR1 Reset value 0026h ISPR2 Reset value 0027h ISPR3 Reset value EICR 0028h Reset value ei1 ei0 ...
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Power saving modes 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Wait), Active Halt and Halt. ...
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ST72321xx-Auto Figure 23. Slow mode clock transitions 8.3 Wait mode Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. ...
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Power saving modes Figure 24. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine ...
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ST72321xx-Auto 8.4 Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active Halt or ...
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Power saving modes Figure 25. Active Halt timing overview 1. This delay occurs only if the MCU exits Active Halt mode by means of a RESET. Figure 26. Active Halt mode flowchart 1. Peripheral clocked with an external clock source ...
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ST72321xx-Auto 8.4.2 Halt mode The Halt mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is cleared (see beeper ...
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Power saving modes Figure 28. Halt mode flowchart 1. WDGHALT is an option bit. See 2. Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such ...
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ST72321xx-Auto Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/O as “Input Pull-up with ...
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I/O ports 9 I/O ports 9.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An ...
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ST72321xx-Auto Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity bits ...
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I/O ports Figure 29. I/O port general block diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 29. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without ...
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ST72321xx-Auto Table 30. I/O port configurations NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS PAD 1. When the ...
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I/O ports Caution: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ADC input, ...
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ST72321xx-Auto Table 31. I/O port configuration (continued) Port Pin name PB7, PB3 Port B PB6:5, PB4, PB2:0 Port C PC7:0 Port D PD7:0 PE7:3, PE1:0 Port E PE2 (Flash devices) PE2 (ROM devices) PF7:3 Port F PF2 PF1:0 9.4 Low ...
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I/O ports Table 34. I/O port register map and reset values (continued) Address (Hex.) Reset value of all I/O port registers 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h Related documentation SPI Communication ...
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ST72321xx-Auto 10 Watchdog timer (WDG) 10.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. ...
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Watchdog timer (WDG) Figure 31. Watchdog block diagram f OSC2 MCC/RTC DIV 64 12-BIT MCC RTC COUNTER MSB 11 6 10.4 How to program the watchdog timeout Figure 32 shows the linear relationship between the 6-bit value to be loaded ...
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ST72321xx-Auto Figure 33. Exact timeout duration (t WHERE (LSB + 128 min0 t = 16384 x t max0 t = 125ns if f OSC2 CNT = Value of T[5:0] bits in the WDGCR register ...
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Watchdog timer (WDG) 10.5 Low power modes Table 35. Effect of low power modes on WDG Mode Slow No effect on Watchdog Wait No effect on Watchdog OIE bit in MCCSR register 0 Halt 0 1 10.6 Hardware watchdog option ...
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ST72321xx-Auto 10.9 Register description 10.9.1 Control register (WDGCR) WDGCR 7 6 WDGA RW Table 36. WDGCR register description Bit Name Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, ...
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Main clock controller with real-time clock and beeper (MCC/RTC) 11 Main clock controller with real-time clock and beeper (MCC/RTC) 11.1 Introduction The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal ...
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ST72321xx-Auto Figure 34. Main clock controller (MCC/RTC) block diagram MCCBCR DIV 64 MCO CP1 MCCSR f OSC2 DIV 11.6 Low power modes Table 38. Effect of low power modes on MCC/RTC Mode Wait Active Halt Halt ...
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Main clock controller with real-time clock and beeper (MCC/RTC) 11.8 Main clock controller registers 11.8.1 MCC control/status register (MCCSR) MCCSR 7 6 MCO RW Table 40. MCCSR register description Bit Name Main clock out selection This bit enables the MCO ...
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ST72321xx-Auto Table 40. MCCSR register description (continued) Bit Name Oscillator interrupt flag This bit is set by hardware and cleared by software reading the MCCSR register. It indicates when set that the main oscillator has reached the selected elapsed time ...
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Main clock controller with real-time clock and beeper (MCC/RTC) Table 44. Main clock controller register map and reset values Address (Hex.) Register label SICSR 002Bh Reset value MCCSR 002Ch Reset value MCCBCR 002Dh Reset value 86/243 ...
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ST72321xx-Auto 12 PWM auto-reload timer (ART) 12.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: ...
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PWM auto-reload timer (ART) 12.2 Functional description 12.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal possible to read or write ...
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ST72321xx-Auto Figure 36. Output compare control f COUNTER COUNTER FDh OCRx PWMDCRx PWMx 12.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing ...
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PWM auto-reload timer (ART) Figure 37. PWM auto-reload timer function 255 DUTY CYCLE REGISTER (PWMDCRx) AUTO-RELOAD REGISTER (ARTARR) 000 WITH OEx=1 AND OPx=0 WITH OEx=1 AND OPx=1 Figure 38. PWM signal from 0% to 100% duty cycle f COUNTER COUNTER ...
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ST72321xx-Auto Figure 39. External event detector example (3 counts EXT COUNTER COUNTER OVF 12.2.8 Input capture function This mode allows the measurement of external signal pulse widths through ARTICRx registers. Each input capture can generate an interrupt ...
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PWM auto-reload timer (ART) 12.2.9 External interrupt capability This mode allows the input capture capabilities to be used as external interrupt sources. The interrupts are generated on the edge of the ARTICx signal. The edge sensitivity of the external interrupts ...
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ST72321xx-Auto 12.3 ART registers 12.3.1 Control/status register (ARTCSR) ARTCSR 7 6 EXCL RW Table 45. ARTCSR register description Bit Name External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit 7 EXCL ...
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PWM auto-reload timer (ART) Table 46. Prescaler selection for ART (continued) f COUNTER INPUT INPUT INPUT INPUT f / 128 INPUT 12.3.2 Counter access register (ARTCAR) ARTCAR 7 ...
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ST72321xx-Auto Table 49. PWM frequency versus resolution ARTARR value 0 [ 0..127 ] [ 128..191 ] [ 192..223 ] [ 224..239 ] 12.3.4 PWM control register (PWMCR) PWMCR 7 6 Table 50. PWMCR register description Bit Name PWM Output Enable ...
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PWM auto-reload timer (ART) 12.3.5 Duty cycle registers (PWMDCRx) PWMDCRx 7 6 Table 52. PWMDCRx register description Bit Name Duty Cycle Data 7:0 DC[7:0] A PWMDCRx register is associated with the OCRx register of each PWM channel to determine the ...
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ST72321xx-Auto 12.3.7 Input capture registers (ARTICRx) ARTICRx 7 6 Table 54. ARTICRx register description Bit Name Input Capture Data 7:0 IC[7:0] Table 55. PWM auto-reload timer register map and reset values Address (Hex.) Register label PWMDCR3 0073h Reset value PWMDCR2 ...
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Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input ...
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ST72321xx-Auto 13.3 Functional description 13.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register ...
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Figure 41. Timer block diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK COUNTER pin REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 (Control/Status Register) ICIE OCIE TOIE FOLV2 (Control Register 1) CR1 ...
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ST72321xx-Auto 16-bit read sequence The 16-bit read sequence (from either the Counter Register or the Alternate Counter Register) is illustrated in Figure 42. 16-bit read sequence The user must read the MS Byte first; the LS Byte value is then ...
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External clock The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition ...
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ST72321xx-Auto 13.3.3 Input capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two 16-bit input capture registers (IC1R and IC2R) are used to latch the ...
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The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activates the input capture function. 6 Moreover if one of the ICAPi pins is configured as an input ...
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ST72321xx-Auto 13.3.4 Output compare In this section, the index, i, may because there are two output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a ...
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If the timer clock is an external clock, the formula is: Where: t = Output compare period (in seconds External timer clock frequency (in hertz) CPU Clearing the output compare interrupt request (that is, clearing the ...
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ST72321xx-Auto Figure 48. Output compare block diagram 16-BIT FREE RUNNING COUNTER 16-bit OUTPUT COMPARE CIRCUIT 16-bit 16-bit OC1R Register OC2R Register Figure 49. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) Figure 50. ...
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One Pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 ...
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ST72321xx-Auto The OC1R register value required for a specific timing application can be calculated using the following formula: Where Pulse period (in seconds CPU clock frequency (in hertz) CPU PRESC = Timer prescaler factor (2, 4 ...
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Figure 53. Pulse width modulation mode timing example with 2 output compare functions COUNTER 34E2 Note: OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1 Note: On timers with only one Output Compare register, a ...
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ST72321xx-Auto Figure 54. Pulse width modulation cycle flowchart If OLVL1 = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal will be ...
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Low power modes Table 56. Effect of low power modes on 16-bit timer Mode No effect on 16-bit timer. Wait Timer interrupts cause the device to exit from Wait mode. 16-bit timer registers are frozen. In Halt ...
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ST72321xx-Auto Table 58. Timer modes Modes One Pulse mode PWM mode 1. See Note 4 in Section 13.3.6 One Pulse mode 2. See Note 5 in Section 13.3.6 One Pulse mode 3. See Note 4 in Section 13.3.7 Pulse width ...
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Table 59. CR1 register description (continued) Bit Name Forced Output Compare 1 This bit is set and cleared by software. 3 FOLV1 0: No effect on the OCMP1 pin 1: Forces OLVL1 to be copied to the OCMP1 ...
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ST72321xx-Auto Table 60. CR2 register description (continued) Bit Name One Pulse Mode 0: One Pulse Mode is not active. 5 OPM 1: One Pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 ...
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Table 62. CSR register description Bit Name Input Capture Flag 1 7 ICF1 Output Compare Flag 1 6 OCF1 Timer Overflow Flag 5 TOF Input Capture Flag 2 4 ICF2 Output Compare Flag 2 3 OCF2 Timer disable ...
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ST72321xx-Auto 13.7.5 Input capture 1 low register (IC1LR) This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). IC1LR 7 6 MSB RO RO 13.7.6 Output compare ...
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Output compare 2 low register (OC2LR) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. OC2LR 7 6 MSB RW RW 13.7.10 Counter high register (CHR) ...
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ST72321xx-Auto 13.7.13 Alternate counter low register (ACLR) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register ...
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Table 63. 16-bit timer register map and reset values Address Register (Hex.) label Timer A: 32 CR1 Timer B: 42 Reset value Timer A: 31 CR2 Timer B: 41 Reset value Timer A: 33 CSR Timer B: 43 ...
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ST72321xx-Auto 14 Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves however the SPI interface cannot be ...
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Serial peripheral interface (SPI) Figure 55. Serial peripheral interface block diagram SPIDR Read Buffer MOSI MISO 8-bit Shift Register SOD bit SCK SS 14.3.1 Functional description A basic example of interconnections between a single master and a single slave is ...
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ST72321xx-Auto Figure 56. Single master/single slave application MASTER MSBit LSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage ...
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Serial peripheral interface (SPI) Figure 57. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA=0) Slave SS (if CPHA=1) Figure 58. Hardware/Software slave select management 14.3.3 Master mode operation In master mode, the serial clock is output on ...
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ST72321xx-Auto 14.3.4 Master mode transmit sequence When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most significant bit first. When data transfer is ...
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Serial peripheral interface (SPI) The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see (OVR) on page 128). 14.4 Clock phase and ...
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ST72321xx-Auto Figure 59. Data clock timing diagram SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit (from master) MOSI MSBit (from slave) SS (to slave) CAPTURE STROBE SCK (CPOL = 1) SCK (CPOL = 0) MISO MSBit (from master) ...
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Serial peripheral interface (SPI) 14.5 Error flags 14.5.1 Master mode fault (MODF) Master mode fault occurs when the master device has its SS pin pulled low. When a Master mode fault occurs: ● The MODF bit is set and an ...
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ST72321xx-Auto Figure 60. Clearing the WCOL bit (Write Collision Flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) Read SPICSR 1st Step 2nd Step Read SPIDR Clearing sequence before SPIF = 1 (during a ...
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Serial peripheral interface (SPI) 14.6 Low power modes Table 64. Effect of low power modes on SPI Mode No effect on SPI. Wait SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. In Halt ...
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ST72321xx-Auto 14.8 SPI registers 14.8.1 Control register (SPICR) SPICR 7 6 SPIE SPE RW RW Table 66. SPICR register description Bit Name Serial Peripheral Interrupt Enable 7 SPIE Serial Peripheral Output Enable 6 SPE Divider Enable 5 SPR2 Master Mode ...
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Serial peripheral interface (SPI) Table 66. SPICR register description (continued) Bit Name Serial Clock Frequency 1:0 SPR[1:0] Table 67. SPI master mode SCK frequency Serial clock f CPU f CPU f CPU f CPU f CPU f CPU 14.8.2 Control/status ...
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ST72321xx-Auto Table 68. SPICSR register description (continued) Bit Name Mode Fault flag This bit is set by hardware when the SS pin is pulled low in master mode (see Master mode fault (MODF) on page SPIE = 1 in the ...
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Serial peripheral interface (SPI) Warning: A read to the SPIDR register returns the value located in the buffer and not the content of the shift register (see Table 69. SPI register map and reset values Address Register (Hex.) SPIDR 0021h ...
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ST72321xx-Auto 15 Serial communications interface (SCI) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range ...
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Serial communications interface (SCI) 15.3 General description The interface is externally connected to another device by two pins (see ● TDO: Transmit Data Output. When the transmitter and the receiver are disabled, the output pin returns to its I/O port ...
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ST72321xx-Auto Figure 62. SCI block diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU Read Received Data Register (RDR) Received Shift Register R8 T8 SCID ...
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Serial communications interface (SCI) 15.4 Functional description The block diagram of the Serial Control Interface, is shown in dedicated registers: ● 2 control registers (SCICR1 and SCICR2) ● a status register (SCISR) ● a baud rate register (SCIBRR) ● an ...
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ST72321xx-Auto 15.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to ...
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Serial communications interface (SCI) bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle characters Setting the TE bit ...
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ST72321xx-Auto When an overrun error occurs: ● The OR bit is set. ● The RDR content is not lost. ● The shift register is overwritten. ● An interrupt is generated if the RIE bit is set and the I bit ...
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Serial communications interface (SCI) Figure 64. SCI baud rate and extended prescaler block diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 SCP1 Framing error A ...
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ST72321xx-Auto Conventional baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with (see SCP[1:0] bits ...
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Serial communications interface (SCI) A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes up by ...
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ST72321xx-Auto Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock ...
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Serial communications interface (SCI) Figure 65. Bit sampling in reception mode RDI LINE Sample clock 15.5 Low power modes Table 71. Effect of low power modes on SCI Mode No effect on SCI. Wait SCI interrupts cause ...
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ST72321xx-Auto Table 72. SCI interrupt control/wake-up capability Interrupt event Idle Line Detected Parity Error 15.7 SCI registers 15.7.1 Status register (SCISR) SCISR 7 6 TDRE Table 73. SCISR register description Bit Name Transmit data register empty This ...
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Serial communications interface (SCI) Table 73. SCISR register description (continued) Bit Name Idle line detect This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the ILIE = 1 in the SCICR2 register. ...
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ST72321xx-Auto 15.7.2 Control register 1 (SCICR1) SCICR1 Table 74. SCICR1 register description Bit Name Receive data bit This bit is used to store the 9th bit of the received word when ...
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Serial communications interface (SCI) Table 74. SCICR1 register description (continued) Bit Name Parity interrupt enable This bit enables the interrupt capability of the hardware parity control when a parity 0 PIE error is detected (PE bit set set ...
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ST72321xx-Auto Table 75. SCICR2 register description (continued) Bit Name Receiver enable This bit enables the receiver set and cleared by software Receiver is disabled 1: Receiver is enabled and begins searching for a start bit ...
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Serial communications interface (SCI) Table 76. SCIBRR register description Bit Name First SCI Prescaler 7:6 SCP[1:0] SCI Transmitter rate divisor 5:3 SCT[2:0] SCI Receiver rate divisor 2:0 SCR[2:0] 15.7.6 Extended receive prescaler division register (SCIERPR) This register allows setting of ...
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ST72321xx-Auto Table 77. SCIERPR register description Bit Name 7:0 ERPR[7:0] 15.7.7 Extended transmit prescaler division register (SCIETPR) This register allows setting of the external prescaler rate division factor for the transmit circuit. SCIETPR 7 6 Table 78. SCIETPR register description ...
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Serial communications interface (SCI) Table 80. SCI register map and reset values Address (Hex.) Register label SCISR 0050h Reset value SCIDR 0051h Reset value SCIBRR 0052h Reset value SCICR1 0053h Reset value SCICR2 0054h Reset value SCIERPR 0055h Reset value ...
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ST72321xx-Auto bus interface (I2C) 16.1 Introduction 2 The I C bus interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I sequencing, ...
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I2C bus interface (I2C) 16.3 General description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by ...
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ST72321xx-Auto 16.3.3 SDA/SCL line control Transmitter mode The interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. Receiver mode The interface holds the clock line low after reception ...
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I2C bus interface (I2C) 16.4 Functional description Refer to the CR, SR1 and SR2 registers default the I C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. ...
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ST72321xx-Auto Closing slave communication After the last data byte is transferred, a Stop Condition is generated by the master. The interface detects this condition and sets: ● EVF and STOPF bits with an interrupt if the ITE bit is set. ...
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I2C bus interface (I2C) Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. ● In 7-bit addressing mode, one address byte is sent. ● In 10-bit addressing mode, sending the first ...
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ST72321xx-Auto Error cases ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will ...
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I2C bus interface (I2C) Figure 68. Transfer sequencing 7-bit Slave receiver: S Address A Data1 EV1 7-bit Slave transmitter: S Address A EV1 EV3 7-bit Master receiver: S Address A EV5 EV6 7-bit Master transmitter: S Address A EV5 EV6 ...
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ST72321xx-Auto 16.5 Low power modes Table 81. Effect of low power modes on I Mode No effect on I Wait interrupts cause the device to exit from Wait mode registers are frozen. In Halt ...
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I2C bus interface (I2C) 16.7 Register description 2 16.7 control register (CR Reserved - Table 83. CR register description Bit Name 7:6 - Reserved. Forced hardware. Peripheral enable This bit is set ...
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ST72321xx-Auto Table 83. CR register description (continued) Bit Name Generation of a Stop condition This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared when the interface ...
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I2C bus interface (I2C) Table 84. SR1 register description (continued) Bit Name 10-bit addressing in Master mode This bit is set by hardware when the master has sent the first byte in 10-bit address mode cleared by software ...
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ST72321xx-Auto Table 84. SR1 register description (continued) Bit Name Master/Slave This bit is set by hardware as soon as the interface is in Master mode (writing START = 1 cleared by hardware after detecting a Stop condition on ...
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I2C bus interface (I2C) Table 85. SR2 register description (continued) Bit Name Arbitration lost This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE = 1. ...
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ST72321xx-Auto Table 86. CCR register description (continued) Bit Name 7-bit clock divider These bits select the speed of the bus (f 6:0 CC[6:0] not cleared when the interface is disabled (PE = 0). Refer to Note: The programmed f 2 ...
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I2C bus interface (I2C) Table 88. OAR1 register description Bit Name Interface address 7:1 ADD[7:1] Address direction bit 0 ADD0 7:0 ADD[7:0] 2 16.7 own address register (OAR2) OAR2 7 6 FR[1:0] RW Table 89. OAR2 register description ...
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ST72321xx-Auto 2 Table 90 register map and reset values Address Register (Hex.) label I2CCR 0018h Reset value I2CSR1 0019h Reset value I2CSR2 001Ah Reset value I2CCCR 001Bh Reset value I2COAR1 001Ch Reset value I2COAR2 001Dh Reset value I2CDR ...
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A/D converter (ADC) 17 10-bit A/D converter (ADC) 17.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input ...
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ST72321xx-Auto 17.3 Functional description The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V conversion result is FFh in the ...
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A/D converter (ADC) 17.3.3 Changing the conversion channel The application can change channels during conversion. When software modifies the CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D converter ...
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ST72321xx-Auto Table 92. ADCCSR register description (continued) Bit Name A/D Converter on This bit is set and cleared by software. 5 ADON 0: Disable ADC and stop conversion 1: Enable ADC and start conversion 4 - Reserved. Must be kept ...
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A/D converter (ADC) 17.6.3 Data register (ADCDRL) ADCDRL 7 6 Table 94. ADCDRL register description Bit Name 7:2 - Reserved. Forced by hardware to 0. 1:0 D[1:0] LSB of Converted Analog Value 17.6.4 ADC register map and reset values ...
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ST72321xx-Auto 18 Instruction set 18.1 CPU addressing modes The CPU features 17 different addressing modes which can be classified in seven main groups as listed in the following table: Table 96. Addressing modes Inherent Immediate Direct Indexed Indirect Relative Bit ...
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Instruction set Table 97. CPU addressing mode overview (continued) Mode Long Indirect Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Bit Indirect 18.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the ...
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ST72321xx-Auto 18.1.2 Immediate Immediate instructions have 2 bytes. The first byte contains the opcode and the second byte contains the operand value. Table 99. Immediate instructions Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC 18.1.3 Direct In ...
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Instruction set 18.1.5 Indirect (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two submodes: Indirect (short) ...
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ST72321xx-Auto Table 100. Instructions supporting direct, indexed, indirect, and indirect indexed addressing modes (continued) Type Short instructions only 18.1.7 Relative (direct, indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to ...
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Instruction set Table 102. Instruction groups (continued) Group Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Condition Code Flag modification 18.2.1 Using a prebyte The instructions ...
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ST72321xx-Auto Table 103. Instruction set overview Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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Instruction set Table 103. Instruction set overview (continued) Mnemo Description JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation ...
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ST72321xx-Auto 19 Electrical characteristics 19.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 19.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical characteristics 19.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure ...
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ST72321xx-Auto 19.2.2 Current characteristics Table 105. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any standard I/O and control pin (2) I Output current sunk by any high ...
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Electrical characteristics 19.3 Operating conditions 19.3.1 General operating conditions Table 107. General operating conditions Symbol f Internal clock frequency CPU Standard voltage range (except Flash Write/Erase Operating voltage for Flash Write/Erase T Ambient temperature range A Note: Some ...
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ST72321xx-Auto 19.3.2 Operating conditions with low voltage detector (LVD) Subject to general operating conditions for V Table 108. Operating conditions with low voltage detector (LVD) Symbol Parameter Reset release threshold V IT+(LVD) (V rise) DD Reset generation threshold V IT-(LVD) ...
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Electrical characteristics 19.3.4 External voltage detector (EVD) thresholds Subject to general operating conditions for V Table 110. External voltage detector (EVD) thresholds Symbol Parameter V 10 AVDF flag toggle threshold (V IT+(EVD) V 01 AVDF flag toggle threshold (V IT-(EVD) ...
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ST72321xx-Auto 19.4 Supply current characteristics The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, the two current values must ...
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Electrical characteristics Power consumption vs f Figure 74. Typical I Figure 75. Typical I Figure 76. Typical I 192/243 : Flash devices CPU in Run mode DD 8MHz 9 4MHz 8 2MHz 1MHz ...
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ST72321xx-Auto Figure 77. Typical I 19.4.2 Supply and clock managers The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To obtain the total device consumption, ...
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Electrical characteristics 19.4.3 On-chip peripherals Measured on LQFP64 generic board T Table 113. On-chip peripherals current consumption Symbol I 16-bit timer supply current DD(TIM) I ART PWM supply current DD(ART) I SPI supply current DD(SPI) I SCI supply current DD(SCI) ...
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ST72321xx-Auto 19.5 Clock and timing characteristics Subject to general operating conditions for V 19.5.1 General timings Table 114. General timings Symbol t Instruction cycle time c(INST) Interrupt reaction time t = t v(IT) t v(IT) 1. Data based on typical ...
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Electrical characteristics 19.5.3 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with four different crystal/ceramic resonator oscillators. All the information given in this paragraph is based on characterization results with specified typical external components. In the ...
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ST72321xx-Auto Table 117. OSCRANGE selection for typical resonators Supplier f (MHz) OSC 2 4 Murata Resonator characteristics given by the ceramic resonator manufacturer. For more information on these resonators, please consult www.murata.com mode is not ...
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Electrical characteristics 19.5.5 PLL characteristics Table 119. PLL characteristics Symbol f PLL input frequency range OSC Instantaneous PLL jitter CPU CPU 1. Data based on characterization results The user must take the PLL jitter into account in ...
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ST72321xx-Auto 19.6 Memory characteristics 19.6.1 RAM and hardware registers Table 120. RAM supply voltage Symbol V Data retention mode RM 1. Minimum V supply voltage without losing data stored in RAM (in Halt mode or under RESET ...
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Electrical characteristics 19.7 EMC (electromagnetic compatibility) characteristics Susceptibilitytests are performed on a sample basis during product characterization. 19.7.1 Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is ...