ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 167

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
16.7.3
Table 84.
I
Table 85.
SR2
2
Bit
7:5
Bit
C status register 2 (SR2)
4
3
1
0
7
STOPF
Name
Name
M/SL
SB
AF
-
SR1 register description (continued)
Reserved
SR2 register description
Master/Slave
Start bit (Master mode)
Reserved. Forced to 0 by hardware.
Acknowledge failure
Stop detection (Slave mode)
This bit is set by hardware as soon as the interface is in Master mode (writing
START = 1). It is cleared by hardware after detecting a Stop condition on the bus or
a loss of arbitration (ARLO = 1). It is also cleared when the interface is disabled
(PE = 0).
0: Slave mode
1: Master mode
This bit is set by hardware as soon as the Start condition is generated (following a
write START = 1). An interrupt is generated if ITE = 1. It is cleared by software
reading SR1 register followed by writing the address byte in DR register. It is also
cleared by hardware when the interface is disabled (PE = 0).
0: No Start condition
1: Start condition generated
This bit is set by hardware when no acknowledge is returned. An interrupt is
generated if ITE = 1. It is cleared by software reading SR2 register or by hardware
when the interface is disabled (PE = 0).
The SCL line is not held low while AF = 1 but by other flags (SB or BTF) that are set
at the same time.
0: No acknowledge failure
1: Acknowledge failure
Note: When an AF event occurs, the SCL line is not held low; however, the SDA line
can remain low if the last bits transmitted are all 0. It is then necessary to release
both lines by software.
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK = 1). An interrupt is generated if ITE = 1. It is cleared by
software reading SR2 register or by hardware when the interface is disabled
(PE = 0).
The SCL line is not held low while STOPF = 1.
0: No Stop condition detected
1: Stop condition detected
6
-
5
Doc ID 13829 Rev 1
RO
AF
4
Function
STOPF
Function
RO
3
ARLO
RO
2
Reset value: 0000 0000 (00h)
I2C bus interface (I2C)
BERR
RO
1
GCAL
167/243
RO
0