ST72321AR9-Auto STMicroelectronics, ST72321AR9-Auto Datasheet - Page 131

• Manufacturer Part Number: ST72321AR9-Auto
• Description: 8-bit MCU for automotive with 60 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72321xx-Auto
14.8
14.8.1
SPI registers
Control register (SPICR)
Table 66.
SPICR
Bit
7
6
5
4
3
2
SPIE
RW
7
MSTR
CPHA
Name
CPOL
SPR2
SPIE
SPE
SPICR register description
SPE
RW
Serial Peripheral Interrupt Enable
Serial Peripheral Output Enable
Divider Enable
Master Mode
Clock Phase
6
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF = 1, MODF = 1 or OVR = 1 in the
SPICSR register.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
is cleared by reset, so the SPI peripheral is not initially connected to the external
pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
This bit is set and cleared by software. It is also cleared by hardware when, in
master mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output
and the functions of the MISO and MOSI pins are reversed.
Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the
serial Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication byte boundaries, the SPI must be
disabled by resetting the SPE bit.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note: The slave must have the same CPOL and CPHA settings as the master.
SPR2
RW
5
Doc ID 13829 Rev 1
MSTR
RW
4
Master mode fault (MODF) on page
Master mode fault (MODF) on page
CPOL
Function
RW
3
Table
Serial peripheral interface (SPI)
CPHA
RW
67.
2
Reset value: 0000 xxxx (0xh)
1
128). The SPE bit
128).
SPR[1:0]
RW
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