ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 219

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
Note:
Normal mode. Before entering Normal mode beCAN always has to synchronize on the CAN
bus. To synchronize, beCAN waits until the CAN bus is idle, this means 11 consecutive
recessive bits have been monitored on CANRX.
Initialization mode
The software initialization can be done while the hardware is in Initialization mode. To enter
this mode the software sets the INRQ bit in the CMCR register and waits until the hardware
has confirmed the request by setting the INAK bit in the CMSR register.
To leave initialization mode, the software clears the INQR bit. beCAN has left initialization
mode once the INAK bit has been cleared by hardware.
While in Initialization mode, all message transfers to and from the CAN bus are stopped and
the status of the CAN bus output CANTX is recessive (high).
Entering initialization mode does not change any of the configuration registers.
To initialize the CAN controller, software has to set up the bit timing registers and the filter
banks. If a filter bank is not used, it is recommended to leave it non active (leave the
corresponding FACT bit cleared).
Normal mode
Once the initialization has been done, the software must request the hardware to enter
Normal mode, to synchronize on the CAN bus and start reception and transmission.
Entering normal mode is done by clearing the INRQ bit in the CMCR register and waiting
until the hardware has confirmed the request by clearing the INAK bit in the CMSR register.
Afterwards, the beCAN synchronizes with the data transfer on the CAN bus by waiting for
the occurrence of a sequence of 11 consecutive recessive bits (≡ bus idle) before it can take
part in bus activities and start message transfer.
The initialization of the filter values is independent from Initialization mode but must be done
while the filter bank is not active (corresponding FACTx bit cleared). The filter bank scale
and mode configuration must be configured in initialization mode.
Low power mode (Sleep)
To reduce power consumption, beCAN has a low power mode called Sleep mode. This
mode is entered on software request by setting the SLEEP bit in the CMCR register. In this
mode, the beCAN clock is stopped. Consequently, software can still access the beCAN
registers and mailboxes but the beCAN will not update the status bits.
Example 1: If software requests entry to initialization mode by setting the INRQ bit while
beCAN is in sleep mode, it will not be acknowledged by the hardware, INAK stays cleared.
beCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on
detection of CAN bus activity.
On CAN bus activity detection, hardware automatically performs the wake-up sequence by
clearing the SLEEP bit if the AWUM bit in the CMCR register is set. If the AWUM bit is
cleared, software has to clear the SLEEP bit when a wake-up interrupt occurs, in order to
exit from sleep mode.
If the wake-up interrupt is enabled (WKUIE bit set in CIER register) a wake-up interrupt will
be generated on detection of CAN bus activity, even if the beCAN automatically performs
the wake-up sequence.
Doc ID 12370 Rev 8
beCAN controller (beCAN)
219/324