ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 115

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

8-BIT A/D CONVERTER (ADC) (Cont’d)
11.8.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
11.8.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in
■
■
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
11.8.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in
tions and to
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
SSA
AIN
Sample capacitor loading [duration: t
During this phase, the V
measured is loaded into the C
capacitor.
A/D conversion [duration: t
During this phase, the A/D conversion is
computed (8 successive approximation cycles)
and the C
from the analog input pin to get the optimum
analog to digital conversion accuracy.
DDA
is the maximum recommended impedance
(low-level voltage reference) then the con-
(high-level voltage reference) then the
ADC
Figure 67
sample capacitor is disconnected
Section 11.8.6
ADC
AIN
Figure
=4/f
AIN
) is lower than or equal to
for the timings.
) is greater than or equal
CPU
AIN
67:
).
CONV
input voltage to be
for the bit defini-
]
ADC
LOAD
sample
Doc ID 7215 Rev 4
]
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
ADC Conversion
In the CSR register:
When a conversion is complete
When the ADON bit is set, ADC performs conver-
sions continuously. Each end of conversion sets
the COCO bit. The COCO bit is cleared by reading
the ADCCSR register.
Figure 67. ADC Conversion Timings
11.8.4 Low Power Modes
Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.
11.8.5 Interrupts
None
WAIT
HALT
ADON
HOLD
CONTROL
– Select the CH[3:0] bits to assign the analog
– Set the ADON bit to enable the A/D converter
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
Mode
channel to be converted.
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
valid until the next conversion has ended.
t
LOAD
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.
t
CONV
COCO BIT SET
Description
ADCCSR READ
OPERATION
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