ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 54
ST72651AR6
Manufacturer Part Number
ST72651AR6
Description
LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
Manufacturer
STMicroelectronics
Datasheet
1.ST72651AR6.pdf
(161 pages)
Specifications of ST72651AR6
Dual Supply Management
analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying
Flash Card I/O lines (voltage shifting)
5 Usb Endpoints
1 control endpoint
Dtc (data Transfer Coprocessor)
Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards
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ST72651AR6
11 ON-CHIP PERIPHERALS
11.1 WATCHDOG TIMER (WDG)
11.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
11.1.2 Main Features
■
■
■
■
11.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 65,536 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.
Figure 33. Watchdog Block Diagram
54/161
1
Programmable free-running downcounter (64
increments of 65536 CPU cycles)
Programmable reset
Reset (if watchdog activated) when the T6 bit
reaches zero
Hardware Watchdog selectable by option byte
f
CPU
WDGA
RESET
T6
T5
WATCHDOG CONTROL REGISTER (CR)
7-BIT DOWNCOUNTER
CLOCK DIVIDER
T4
Doc ID 7215 Rev 4
÷65536
T3
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: it counts down even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
– The T[5:0] bits contain the number of increments
Table 17.Watchdog Timing (f
diate reset
which represents the time delay before the
watchdog produces a reset.
Max
T2
Min
T1
CR Register
initial value
T0
C0h
FFh
WDG timeout period
CPU
= 8 MHz)
524.288
Table
8.192
(ms)
17):
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